clk/mediatek/clk-mt8195-img.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // Copyright (c) 2021 MediaTek Inc.
0004 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
0005
0006 #include "clk-gate.h"
0007 #include "clk-mtk.h"
0008
0009 #include <dt-bindings/clock/mt8195-clk.h>
0010 #include <linux/clk-provider.h>
0011 #include <linux/platform_device.h>
0012
0013 static const struct mtk_gate_regs img_cg_regs = {
0014     .set_ofs = 0x4,
0015     .clr_ofs = 0x8,
0016     .sta_ofs = 0x0,
0017 };
0018
0019 #define GATE_IMG(_id, _name, _parent, _shift)           \
0020     GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
0021
0022 static const struct mtk_gate img_clks[] = {
0023     GATE_IMG(CLK_IMG_LARB9, "img_larb9", "top_img", 0),
0024     GATE_IMG(CLK_IMG_TRAW0, "img_traw0", "top_img", 1),
0025     GATE_IMG(CLK_IMG_TRAW1, "img_traw1", "top_img", 2),
0026     GATE_IMG(CLK_IMG_TRAW2, "img_traw2", "top_img", 3),
0027     GATE_IMG(CLK_IMG_TRAW3, "img_traw3", "top_img", 4),
0028     GATE_IMG(CLK_IMG_DIP0, "img_dip0", "top_img", 8),
0029     GATE_IMG(CLK_IMG_WPE0, "img_wpe0", "top_img", 9),
0030     GATE_IMG(CLK_IMG_IPE, "img_ipe", "top_img", 10),
0031     GATE_IMG(CLK_IMG_DIP1, "img_dip1", "top_img", 11),
0032     GATE_IMG(CLK_IMG_WPE1, "img_wpe1", "top_img", 12),
0033     GATE_IMG(CLK_IMG_GALS, "img_gals", "top_img", 31),
0034 };
0035
0036 static const struct mtk_gate img1_dip_top_clks[] = {
0037     GATE_IMG(CLK_IMG1_DIP_TOP_LARB10, "img1_dip_top_larb10", "top_img", 0),
0038     GATE_IMG(CLK_IMG1_DIP_TOP_DIP_TOP, "img1_dip_top_dip_top", "top_img", 1),
0039 };
0040
0041 static const struct mtk_gate img1_dip_nr_clks[] = {
0042     GATE_IMG(CLK_IMG1_DIP_NR_RESERVE, "img1_dip_nr_reserve", "top_img", 0),
0043     GATE_IMG(CLK_IMG1_DIP_NR_DIP_NR, "img1_dip_nr_dip_nr", "top_img", 1),
0044 };
0045
0046 static const struct mtk_gate img1_wpe_clks[] = {
0047     GATE_IMG(CLK_IMG1_WPE_LARB11, "img1_wpe_larb11", "top_img", 0),
0048     GATE_IMG(CLK_IMG1_WPE_WPE, "img1_wpe_wpe", "top_img", 1),
0049 };
0050
0051 static const struct mtk_clk_desc img_desc = {
0052     .clks = img_clks,
0053     .num_clks = ARRAY_SIZE(img_clks),
0054 };
0055
0056 static const struct mtk_clk_desc img1_dip_top_desc = {
0057     .clks = img1_dip_top_clks,
0058     .num_clks = ARRAY_SIZE(img1_dip_top_clks),
0059 };
0060
0061 static const struct mtk_clk_desc img1_dip_nr_desc = {
0062     .clks = img1_dip_nr_clks,
0063     .num_clks = ARRAY_SIZE(img1_dip_nr_clks),
0064 };
0065
0066 static const struct mtk_clk_desc img1_wpe_desc = {
0067     .clks = img1_wpe_clks,
0068     .num_clks = ARRAY_SIZE(img1_wpe_clks),
0069 };
0070
0071 static const struct of_device_id of_match_clk_mt8195_img[] = {
0072     {
0073         .compatible = "mediatek,mt8195-imgsys",
0074         .data = &img_desc,
0075     }, {
0076         .compatible = "mediatek,mt8195-imgsys1_dip_top",
0077         .data = &img1_dip_top_desc,
0078     }, {
0079         .compatible = "mediatek,mt8195-imgsys1_dip_nr",
0080         .data = &img1_dip_nr_desc,
0081     }, {
0082         .compatible = "mediatek,mt8195-imgsys1_wpe",
0083         .data = &img1_wpe_desc,
0084     }, {
0085         /* sentinel */
0086     }
0087 };
0088
0089 static struct platform_driver clk_mt8195_img_drv = {
0090     .probe = mtk_clk_simple_probe,
0091     .remove = mtk_clk_simple_remove,
0092     .driver = {
0093         .name = "clk-mt8195-img",
0094         .of_match_table = of_match_clk_mt8195_img,
0095     },
0096 };
0097 builtin_platform_driver(clk_mt8195_img_drv);