clk/mediatek/clk-mt8195-ccu.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // Copyright (c) 2021 MediaTek Inc.
0004 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
0005
0006 #include "clk-gate.h"
0007 #include "clk-mtk.h"
0008
0009 #include <dt-bindings/clock/mt8195-clk.h>
0010 #include <linux/clk-provider.h>
0011 #include <linux/platform_device.h>
0012
0013 static const struct mtk_gate_regs ccu_cg_regs = {
0014     .set_ofs = 0x4,
0015     .clr_ofs = 0x8,
0016     .sta_ofs = 0x0,
0017 };
0018
0019 #define GATE_CCU(_id, _name, _parent, _shift)           \
0020     GATE_MTK(_id, _name, _parent, &ccu_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
0021
0022 static const struct mtk_gate ccu_clks[] = {
0023     GATE_CCU(CLK_CCU_LARB18, "ccu_larb18", "top_ccu", 0),
0024     GATE_CCU(CLK_CCU_AHB, "ccu_ahb", "top_ccu", 1),
0025     GATE_CCU(CLK_CCU_CCU0, "ccu_ccu0", "top_ccu", 2),
0026     GATE_CCU(CLK_CCU_CCU1, "ccu_ccu1", "top_ccu", 3),
0027 };
0028
0029 static const struct mtk_clk_desc ccu_desc = {
0030     .clks = ccu_clks,
0031     .num_clks = ARRAY_SIZE(ccu_clks),
0032 };
0033
0034 static const struct of_device_id of_match_clk_mt8195_ccu[] = {
0035     {
0036         .compatible = "mediatek,mt8195-ccusys",
0037         .data = &ccu_desc,
0038     }, {
0039         /* sentinel */
0040     }
0041 };
0042
0043 static struct platform_driver clk_mt8195_ccu_drv = {
0044     .probe = mtk_clk_simple_probe,
0045     .remove = mtk_clk_simple_remove,
0046     .driver = {
0047         .name = "clk-mt8195-ccu",
0048         .of_match_table = of_match_clk_mt8195_ccu,
0049     },
0050 };
0051 builtin_platform_driver(clk_mt8195_ccu_drv);