clk/mediatek/clk-mt8195-apmixedsys.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // Copyright (c) 2021 MediaTek Inc.
0004 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
0005
0006 #include "clk-gate.h"
0007 #include "clk-mtk.h"
0008 #include "clk-pll.h"
0009
0010 #include <dt-bindings/clock/mt8195-clk.h>
0011 #include <linux/of_device.h>
0012 #include <linux/platform_device.h>
0013
0014 static const struct mtk_gate_regs apmixed_cg_regs = {
0015     .set_ofs = 0x8,
0016     .clr_ofs = 0x8,
0017     .sta_ofs = 0x8,
0018 };
0019
0020 #define GATE_APMIXED(_id, _name, _parent, _shift)           \
0021     GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
0022
0023 static const struct mtk_gate apmixed_clks[] = {
0024     GATE_APMIXED(CLK_APMIXED_PLL_SSUSB26M, "pll_ssusb26m", "clk26m", 1),
0025 };
0026
0027 #define MT8195_PLL_FMAX     (3800UL * MHZ)
0028 #define MT8195_PLL_FMIN     (1500UL * MHZ)
0029 #define MT8195_INTEGER_BITS 8
0030
0031 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags,       \
0032         _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift,        \
0033         _tuner_reg, _tuner_en_reg, _tuner_en_bit,           \
0034         _pcw_reg, _pcw_shift, _pcw_chg_reg,             \
0035         _en_reg, _pll_en_bit) {                 \
0036         .id = _id,                      \
0037         .name = _name,                      \
0038         .reg = _reg,                        \
0039         .pwr_reg = _pwr_reg,                    \
0040         .en_mask = _en_mask,                    \
0041         .flags = _flags,                    \
0042         .rst_bar_mask = _rst_bar_mask,              \
0043         .fmax = MT8195_PLL_FMAX,                \
0044         .fmin = MT8195_PLL_FMIN,                \
0045         .pcwbits = _pcwbits,                    \
0046         .pcwibits = MT8195_INTEGER_BITS,            \
0047         .pd_reg = _pd_reg,                  \
0048         .pd_shift = _pd_shift,                  \
0049         .tuner_reg = _tuner_reg,                \
0050         .tuner_en_reg = _tuner_en_reg,              \
0051         .tuner_en_bit = _tuner_en_bit,              \
0052         .pcw_reg = _pcw_reg,                    \
0053         .pcw_shift = _pcw_shift,                \
0054         .pcw_chg_reg = _pcw_chg_reg,                \
0055         .en_reg = _en_reg,                  \
0056         .pll_en_bit = _pll_en_bit,              \
0057     }
0058
0059 static const struct mtk_pll_data plls[] = {
0060     PLL(CLK_APMIXED_NNAPLL, "nnapll", 0x0390, 0x03a0, 0,
0061         0, 0, 22, 0x0398, 24, 0, 0, 0, 0x0398, 0, 0x0398, 0, 9),
0062     PLL(CLK_APMIXED_RESPLL, "respll", 0x0190, 0x0320, 0,
0063         0, 0, 22, 0x0198, 24, 0, 0, 0, 0x0198, 0, 0x0198, 0, 9),
0064     PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x0360, 0x0370, 0,
0065         0, 0, 22, 0x0368, 24, 0, 0, 0, 0x0368, 0, 0x0368, 0, 9),
0066     PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0710, 0x0720, 0,
0067         0, 0, 22, 0x0718, 24, 0, 0, 0, 0x0718, 0, 0x0718, 0, 9),
0068     PLL(CLK_APMIXED_TVDPLL1, "tvdpll1", 0x00a0, 0x00b0, 0,
0069         0, 0, 22, 0x00a8, 24, 0, 0, 0, 0x00a8, 0, 0x00a8, 0, 9),
0070     PLL(CLK_APMIXED_TVDPLL2, "tvdpll2", 0x00c0, 0x00d0, 0,
0071         0, 0, 22, 0x00c8, 24, 0, 0, 0, 0x00c8, 0, 0x00c8, 0, 9),
0072     PLL(CLK_APMIXED_MMPLL, "mmpll", 0x00e0, 0x00f0, 0xff000000,
0073         HAVE_RST_BAR, BIT(23), 22, 0x00e8, 24, 0, 0, 0, 0x00e8, 0, 0x00e8, 0, 9),
0074     PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x01d0, 0x01e0, 0xff000000,
0075         HAVE_RST_BAR, BIT(23), 22, 0x01d8, 24, 0, 0, 0, 0x01d8, 0, 0x01d8, 0, 9),
0076     PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x0890, 0x08a0, 0,
0077         0, 0, 22, 0x0898, 24, 0, 0, 0, 0x0898, 0, 0x0898, 0, 9),
0078     PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0100, 0x0110, 0,
0079         0, 0, 22, 0x0108, 24, 0, 0, 0, 0x0108, 0, 0x0108, 0, 9),
0080     PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x01f0, 0x0700, 0xff000000,
0081         HAVE_RST_BAR, BIT(23), 22, 0x01f8, 24, 0, 0, 0, 0x01f8, 0, 0x01f8, 0, 9),
0082     PLL(CLK_APMIXED_HDMIPLL1, "hdmipll1", 0x08c0, 0x08d0, 0,
0083         0, 0, 22, 0x08c8, 24, 0, 0, 0, 0x08c8, 0, 0x08c8, 0, 9),
0084     PLL(CLK_APMIXED_HDMIPLL2, "hdmipll2", 0x0870, 0x0880, 0,
0085         0, 0, 22, 0x0878, 24, 0, 0, 0, 0x0878, 0, 0x0878, 0, 9),
0086     PLL(CLK_APMIXED_HDMIRX_APLL, "hdmirx_apll", 0x08e0, 0x0dd4, 0,
0087         0, 0, 32, 0x08e8, 24, 0, 0, 0, 0x08ec, 0, 0x08e8, 0, 9),
0088     PLL(CLK_APMIXED_USB1PLL, "usb1pll", 0x01a0, 0x01b0, 0,
0089         0, 0, 22, 0x01a8, 24, 0, 0, 0, 0x01a8, 0, 0x01a8, 0, 9),
0090     PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x07e0, 0x07f0, 0,
0091         0, 0, 22, 0x07e8, 24, 0, 0, 0, 0x07e8, 0, 0x07e8, 0, 9),
0092     PLL(CLK_APMIXED_APLL1, "apll1", 0x07c0, 0x0dc0, 0,
0093         0, 0, 32, 0x07c8, 24, 0x0470, 0x0000, 12, 0x07cc, 0, 0x07c8, 0, 9),
0094     PLL(CLK_APMIXED_APLL2, "apll2", 0x0780, 0x0dc4, 0,
0095         0, 0, 32, 0x0788, 24, 0x0474, 0x0000, 13, 0x078c, 0, 0x0788, 0, 9),
0096     PLL(CLK_APMIXED_APLL3, "apll3", 0x0760, 0x0dc8, 0,
0097         0, 0, 32, 0x0768, 24, 0x0478, 0x0000, 14, 0x076c, 0, 0x0768, 0, 9),
0098     PLL(CLK_APMIXED_APLL4, "apll4", 0x0740, 0x0dcc, 0,
0099         0, 0, 32, 0x0748, 24, 0x047C, 0x0000, 15, 0x074c, 0, 0x0748, 0, 9),
0100     PLL(CLK_APMIXED_APLL5, "apll5", 0x07a0, 0x0dd0, 0x100000,
0101         0, 0, 32, 0x07a8, 24, 0x0480, 0x0000, 16, 0x07ac, 0, 0x07a8, 0, 9),
0102     PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0340, 0x0350, 0,
0103         0, 0, 22, 0x0348, 24, 0, 0, 0, 0x0348, 0, 0x0348, 0, 9),
0104     PLL(CLK_APMIXED_DGIPLL, "dgipll", 0x0150, 0x0160, 0,
0105         0, 0, 22, 0x0158, 24, 0, 0, 0, 0x0158, 0, 0x0158, 0, 9),
0106 };
0107
0108 static const struct of_device_id of_match_clk_mt8195_apmixed[] = {
0109     { .compatible = "mediatek,mt8195-apmixedsys", },
0110     {}
0111 };
0112
0113 static int clk_mt8195_apmixed_probe(struct platform_device *pdev)
0114 {
0115     struct clk_hw_onecell_data *clk_data;
0116     struct device_node *node = pdev->dev.of_node;
0117     int r;
0118
0119     clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
0120     if (!clk_data)
0121         return -ENOMEM;
0122
0123     r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
0124     if (r)
0125         goto free_apmixed_data;
0126
0127     r = mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
0128     if (r)
0129         goto unregister_plls;
0130
0131     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0132     if (r)
0133         goto unregister_gates;
0134
0135     platform_set_drvdata(pdev, clk_data);
0136
0137     return r;
0138
0139 unregister_gates:
0140     mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
0141 unregister_plls:
0142     mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
0143 free_apmixed_data:
0144     mtk_free_clk_data(clk_data);
0145     return r;
0146 }
0147
0148 static int clk_mt8195_apmixed_remove(struct platform_device *pdev)
0149 {
0150     struct device_node *node = pdev->dev.of_node;
0151     struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
0152
0153     of_clk_del_provider(node);
0154     mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
0155     mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
0156     mtk_free_clk_data(clk_data);
0157
0158     return 0;
0159 }
0160
0161 static struct platform_driver clk_mt8195_apmixed_drv = {
0162     .probe = clk_mt8195_apmixed_probe,
0163     .remove = clk_mt8195_apmixed_remove,
0164     .driver = {
0165         .name = "clk-mt8195-apmixed",
0166         .of_match_table = of_match_clk_mt8195_apmixed,
0167     },
0168 };
0169 builtin_platform_driver(clk_mt8195_apmixed_drv);