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0006 #include <linux/clk.h>
0007 #include <linux/delay.h>
0008 #include <linux/mfd/syscon.h>
0009 #include <linux/of.h>
0010 #include <linux/of_address.h>
0011 #include <linux/of_device.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/slab.h>
0014
0015 #include "clk-gate.h"
0016 #include "clk-mtk.h"
0017 #include "clk-mux.h"
0018 #include "clk-pll.h"
0019
0020 #include <dt-bindings/clock/mt8192-clk.h>
0021 #include <dt-bindings/reset/mt8192-resets.h>
0022
0023 static DEFINE_SPINLOCK(mt8192_clk_lock);
0024
0025 static const struct mtk_fixed_clk top_fixed_clks[] = {
0026 FIXED_CLK(CLK_TOP_ULPOSC, "ulposc", NULL, 260000000),
0027 };
0028
0029 static const struct mtk_fixed_factor top_early_divs[] = {
0030 FACTOR(CLK_TOP_CSW_F26M_D2, "csw_f26m_d2", "clk26m", 1, 2),
0031 };
0032
0033 static const struct mtk_fixed_factor top_divs[] = {
0034 FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
0035 FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4),
0036 FACTOR(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2),
0037 FACTOR(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4),
0038 FACTOR(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8),
0039 FACTOR(CLK_TOP_MAINPLL_D4_D16, "mainpll_d4_d16", "mainpll_d4", 1, 16),
0040 FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
0041 FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2),
0042 FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4),
0043 FACTOR(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8),
0044 FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6),
0045 FACTOR(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2),
0046 FACTOR(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4),
0047 FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
0048 FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2),
0049 FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4),
0050 FACTOR(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8),
0051 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
0052 FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
0053 FACTOR(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2),
0054 FACTOR(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4),
0055 FACTOR(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8),
0056 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
0057 FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2),
0058 FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
0059 FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8),
0060 FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6),
0061 FACTOR(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2),
0062 FACTOR(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4),
0063 FACTOR(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8),
0064 FACTOR(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll_d6", 1, 16),
0065 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
0066 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
0067 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2),
0068 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
0069 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8),
0070 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
0071 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
0072 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
0073 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8),
0074 FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
0075 FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2),
0076 FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
0077 FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2),
0078 FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6),
0079 FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll_d6", 1, 2),
0080 FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
0081 FACTOR(CLK_TOP_MMPLL_D9, "mmpll_d9", "mmpll", 1, 9),
0082 FACTOR(CLK_TOP_APUPLL, "apupll_ck", "apupll", 1, 2),
0083 FACTOR(CLK_TOP_NPUPLL, "npupll_ck", "npupll", 1, 1),
0084 FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1),
0085 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2),
0086 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
0087 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8),
0088 FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16),
0089 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
0090 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
0091 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
0092 FACTOR(CLK_TOP_OSC_D2, "osc_d2", "ulposc", 1, 2),
0093 FACTOR(CLK_TOP_OSC_D4, "osc_d4", "ulposc", 1, 4),
0094 FACTOR(CLK_TOP_OSC_D8, "osc_d8", "ulposc", 1, 8),
0095 FACTOR(CLK_TOP_OSC_D10, "osc_d10", "ulposc", 1, 10),
0096 FACTOR(CLK_TOP_OSC_D16, "osc_d16", "ulposc", 1, 16),
0097 FACTOR(CLK_TOP_OSC_D20, "osc_d20", "ulposc", 1, 20),
0098 FACTOR(CLK_TOP_ADSPPLL, "adsppll_ck", "adsppll", 1, 1),
0099 FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13),
0100 FACTOR(CLK_TOP_UNIVPLL_192M_D2, "univpll_192m_d2", "univpll_192m", 1, 2),
0101 FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4),
0102 FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8),
0103 FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16),
0104 FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32),
0105 };
0106
0107 static const char * const axi_parents[] = {
0108 "clk26m",
0109 "mainpll_d4_d4",
0110 "mainpll_d7_d2",
0111 "mainpll_d4_d2",
0112 "mainpll_d5_d2",
0113 "mainpll_d6_d2",
0114 "osc_d4"
0115 };
0116
0117 static const char * const spm_parents[] = {
0118 "clk26m",
0119 "osc_d10",
0120 "mainpll_d7_d4",
0121 "clk32k"
0122 };
0123
0124 static const char * const scp_parents[] = {
0125 "clk26m",
0126 "univpll_d5",
0127 "mainpll_d6_d2",
0128 "mainpll_d6",
0129 "univpll_d6",
0130 "mainpll_d4_d2",
0131 "mainpll_d5_d2",
0132 "univpll_d4_d2"
0133 };
0134
0135 static const char * const bus_aximem_parents[] = {
0136 "clk26m",
0137 "mainpll_d7_d2",
0138 "mainpll_d4_d2",
0139 "mainpll_d5_d2",
0140 "mainpll_d6"
0141 };
0142
0143 static const char * const disp_parents[] = {
0144 "clk26m",
0145 "univpll_d6_d2",
0146 "mainpll_d5_d2",
0147 "mmpll_d6_d2",
0148 "univpll_d5_d2",
0149 "univpll_d4_d2",
0150 "mmpll_d7",
0151 "univpll_d6",
0152 "mainpll_d4",
0153 "mmpll_d5_d2"
0154 };
0155
0156 static const char * const mdp_parents[] = {
0157 "clk26m",
0158 "mainpll_d5_d2",
0159 "mmpll_d6_d2",
0160 "mainpll_d4_d2",
0161 "mmpll_d4_d2",
0162 "mainpll_d6",
0163 "univpll_d6",
0164 "mainpll_d4",
0165 "tvdpll_ck",
0166 "univpll_d4",
0167 "mmpll_d5_d2"
0168 };
0169
0170 static const char * const img1_parents[] = {
0171 "clk26m",
0172 "univpll_d4",
0173 "tvdpll_ck",
0174 "mainpll_d4",
0175 "univpll_d5",
0176 "mmpll_d6",
0177 "univpll_d6",
0178 "mainpll_d6",
0179 "mmpll_d4_d2",
0180 "mainpll_d4_d2",
0181 "mmpll_d6_d2",
0182 "mmpll_d5_d2"
0183 };
0184
0185 static const char * const img2_parents[] = {
0186 "clk26m",
0187 "univpll_d4",
0188 "tvdpll_ck",
0189 "mainpll_d4",
0190 "univpll_d5",
0191 "mmpll_d6",
0192 "univpll_d6",
0193 "mainpll_d6",
0194 "mmpll_d4_d2",
0195 "mainpll_d4_d2",
0196 "mmpll_d6_d2",
0197 "mmpll_d5_d2"
0198 };
0199
0200 static const char * const ipe_parents[] = {
0201 "clk26m",
0202 "mainpll_d4",
0203 "mmpll_d6",
0204 "univpll_d6",
0205 "mainpll_d6",
0206 "univpll_d4_d2",
0207 "mainpll_d4_d2",
0208 "mmpll_d6_d2",
0209 "mmpll_d5_d2"
0210 };
0211
0212 static const char * const dpe_parents[] = {
0213 "clk26m",
0214 "mainpll_d4",
0215 "mmpll_d6",
0216 "univpll_d6",
0217 "mainpll_d6",
0218 "univpll_d4_d2",
0219 "univpll_d5_d2",
0220 "mmpll_d6_d2"
0221 };
0222
0223 static const char * const cam_parents[] = {
0224 "clk26m",
0225 "mainpll_d4",
0226 "mmpll_d6",
0227 "univpll_d4",
0228 "univpll_d5",
0229 "univpll_d6",
0230 "mmpll_d7",
0231 "univpll_d4_d2",
0232 "mainpll_d4_d2",
0233 "univpll_d6_d2"
0234 };
0235
0236 static const char * const ccu_parents[] = {
0237 "clk26m",
0238 "mainpll_d4",
0239 "mmpll_d6",
0240 "mainpll_d6",
0241 "mmpll_d7",
0242 "univpll_d4_d2",
0243 "mmpll_d6_d2",
0244 "mmpll_d5_d2",
0245 "univpll_d5",
0246 "univpll_d6_d2"
0247 };
0248
0249 static const char * const dsp7_parents[] = {
0250 "clk26m",
0251 "mainpll_d4_d2",
0252 "mainpll_d6",
0253 "mmpll_d6",
0254 "univpll_d5",
0255 "mmpll_d5",
0256 "univpll_d4",
0257 "mmpll_d4"
0258 };
0259
0260 static const char * const mfg_ref_parents[] = {
0261 "clk26m",
0262 "clk26m",
0263 "univpll_d6",
0264 "mainpll_d5_d2"
0265 };
0266
0267 static const char * const mfg_pll_parents[] = {
0268 "mfg_ref_sel",
0269 "mfgpll"
0270 };
0271
0272 static const char * const camtg_parents[] = {
0273 "clk26m",
0274 "univpll_192m_d8",
0275 "univpll_d6_d8",
0276 "univpll_192m_d4",
0277 "univpll_d6_d16",
0278 "csw_f26m_d2",
0279 "univpll_192m_d16",
0280 "univpll_192m_d32"
0281 };
0282
0283 static const char * const camtg2_parents[] = {
0284 "clk26m",
0285 "univpll_192m_d8",
0286 "univpll_d6_d8",
0287 "univpll_192m_d4",
0288 "univpll_d6_d16",
0289 "csw_f26m_d2",
0290 "univpll_192m_d16",
0291 "univpll_192m_d32"
0292 };
0293
0294 static const char * const camtg3_parents[] = {
0295 "clk26m",
0296 "univpll_192m_d8",
0297 "univpll_d6_d8",
0298 "univpll_192m_d4",
0299 "univpll_d6_d16",
0300 "csw_f26m_d2",
0301 "univpll_192m_d16",
0302 "univpll_192m_d32"
0303 };
0304
0305 static const char * const camtg4_parents[] = {
0306 "clk26m",
0307 "univpll_192m_d8",
0308 "univpll_d6_d8",
0309 "univpll_192m_d4",
0310 "univpll_d6_d16",
0311 "csw_f26m_d2",
0312 "univpll_192m_d16",
0313 "univpll_192m_d32"
0314 };
0315
0316 static const char * const camtg5_parents[] = {
0317 "clk26m",
0318 "univpll_192m_d8",
0319 "univpll_d6_d8",
0320 "univpll_192m_d4",
0321 "univpll_d6_d16",
0322 "csw_f26m_d2",
0323 "univpll_192m_d16",
0324 "univpll_192m_d32"
0325 };
0326
0327 static const char * const camtg6_parents[] = {
0328 "clk26m",
0329 "univpll_192m_d8",
0330 "univpll_d6_d8",
0331 "univpll_192m_d4",
0332 "univpll_d6_d16",
0333 "csw_f26m_d2",
0334 "univpll_192m_d16",
0335 "univpll_192m_d32"
0336 };
0337
0338 static const char * const uart_parents[] = {
0339 "clk26m",
0340 "univpll_d6_d8"
0341 };
0342
0343 static const char * const spi_parents[] = {
0344 "clk26m",
0345 "mainpll_d5_d4",
0346 "mainpll_d6_d4",
0347 "msdcpll_d4"
0348 };
0349
0350 static const char * const msdc50_0_h_parents[] = {
0351 "clk26m",
0352 "mainpll_d4_d2",
0353 "mainpll_d6_d2"
0354 };
0355
0356 static const char * const msdc50_0_parents[] = {
0357 "clk26m",
0358 "msdcpll_ck",
0359 "msdcpll_d2",
0360 "univpll_d4_d4",
0361 "mainpll_d6_d2",
0362 "univpll_d4_d2"
0363 };
0364
0365 static const char * const msdc30_1_parents[] = {
0366 "clk26m",
0367 "univpll_d6_d2",
0368 "mainpll_d6_d2",
0369 "mainpll_d7_d2",
0370 "msdcpll_d2"
0371 };
0372
0373 static const char * const msdc30_2_parents[] = {
0374 "clk26m",
0375 "univpll_d6_d2",
0376 "mainpll_d6_d2",
0377 "mainpll_d7_d2",
0378 "msdcpll_d2"
0379 };
0380
0381 static const char * const audio_parents[] = {
0382 "clk26m",
0383 "mainpll_d5_d8",
0384 "mainpll_d7_d8",
0385 "mainpll_d4_d16"
0386 };
0387
0388 static const char * const aud_intbus_parents[] = {
0389 "clk26m",
0390 "mainpll_d4_d4",
0391 "mainpll_d7_d4"
0392 };
0393
0394 static const char * const pwrap_ulposc_parents[] = {
0395 "osc_d10",
0396 "clk26m",
0397 "osc_d4",
0398 "osc_d8",
0399 "osc_d16"
0400 };
0401
0402 static const char * const atb_parents[] = {
0403 "clk26m",
0404 "mainpll_d4_d2",
0405 "mainpll_d5_d2"
0406 };
0407
0408 static const char * const dpi_parents[] = {
0409 "clk26m",
0410 "tvdpll_d2",
0411 "tvdpll_d4",
0412 "tvdpll_d8",
0413 "tvdpll_d16"
0414 };
0415
0416 static const char * const scam_parents[] = {
0417 "clk26m",
0418 "mainpll_d5_d4"
0419 };
0420
0421 static const char * const disp_pwm_parents[] = {
0422 "clk26m",
0423 "univpll_d6_d4",
0424 "osc_d2",
0425 "osc_d4",
0426 "osc_d16"
0427 };
0428
0429 static const char * const usb_top_parents[] = {
0430 "clk26m",
0431 "univpll_d5_d4",
0432 "univpll_d6_d4",
0433 "univpll_d5_d2"
0434 };
0435
0436 static const char * const ssusb_xhci_parents[] = {
0437 "clk26m",
0438 "univpll_d5_d4",
0439 "univpll_d6_d4",
0440 "univpll_d5_d2"
0441 };
0442
0443 static const char * const i2c_parents[] = {
0444 "clk26m",
0445 "mainpll_d4_d8",
0446 "univpll_d5_d4"
0447 };
0448
0449 static const char * const seninf_parents[] = {
0450 "clk26m",
0451 "univpll_d4_d4",
0452 "univpll_d6_d2",
0453 "univpll_d4_d2",
0454 "univpll_d7",
0455 "univpll_d6",
0456 "mmpll_d6",
0457 "univpll_d5"
0458 };
0459
0460 static const char * const seninf1_parents[] = {
0461 "clk26m",
0462 "univpll_d4_d4",
0463 "univpll_d6_d2",
0464 "univpll_d4_d2",
0465 "univpll_d7",
0466 "univpll_d6",
0467 "mmpll_d6",
0468 "univpll_d5"
0469 };
0470
0471 static const char * const seninf2_parents[] = {
0472 "clk26m",
0473 "univpll_d4_d4",
0474 "univpll_d6_d2",
0475 "univpll_d4_d2",
0476 "univpll_d7",
0477 "univpll_d6",
0478 "mmpll_d6",
0479 "univpll_d5"
0480 };
0481
0482 static const char * const seninf3_parents[] = {
0483 "clk26m",
0484 "univpll_d4_d4",
0485 "univpll_d6_d2",
0486 "univpll_d4_d2",
0487 "univpll_d7",
0488 "univpll_d6",
0489 "mmpll_d6",
0490 "univpll_d5"
0491 };
0492
0493 static const char * const tl_parents[] = {
0494 "clk26m",
0495 "univpll_192m_d2",
0496 "mainpll_d6_d4"
0497 };
0498
0499 static const char * const dxcc_parents[] = {
0500 "clk26m",
0501 "mainpll_d4_d2",
0502 "mainpll_d4_d4",
0503 "mainpll_d4_d8"
0504 };
0505
0506 static const char * const aud_engen1_parents[] = {
0507 "clk26m",
0508 "apll1_d2",
0509 "apll1_d4",
0510 "apll1_d8"
0511 };
0512
0513 static const char * const aud_engen2_parents[] = {
0514 "clk26m",
0515 "apll2_d2",
0516 "apll2_d4",
0517 "apll2_d8"
0518 };
0519
0520 static const char * const aes_ufsfde_parents[] = {
0521 "clk26m",
0522 "mainpll_d4",
0523 "mainpll_d4_d2",
0524 "mainpll_d6",
0525 "mainpll_d4_d4",
0526 "univpll_d4_d2",
0527 "univpll_d6"
0528 };
0529
0530 static const char * const ufs_parents[] = {
0531 "clk26m",
0532 "mainpll_d4_d4",
0533 "mainpll_d4_d8",
0534 "univpll_d4_d4",
0535 "mainpll_d6_d2",
0536 "mainpll_d5_d2",
0537 "msdcpll_d2"
0538 };
0539
0540 static const char * const aud_1_parents[] = {
0541 "clk26m",
0542 "apll1_ck"
0543 };
0544
0545 static const char * const aud_2_parents[] = {
0546 "clk26m",
0547 "apll2_ck"
0548 };
0549
0550 static const char * const adsp_parents[] = {
0551 "clk26m",
0552 "mainpll_d6",
0553 "mainpll_d5_d2",
0554 "univpll_d4_d4",
0555 "univpll_d4",
0556 "univpll_d6",
0557 "ulposc",
0558 "adsppll_ck"
0559 };
0560
0561 static const char * const dpmaif_main_parents[] = {
0562 "clk26m",
0563 "univpll_d4_d4",
0564 "mainpll_d6",
0565 "mainpll_d4_d2",
0566 "univpll_d4_d2"
0567 };
0568
0569 static const char * const venc_parents[] = {
0570 "clk26m",
0571 "mmpll_d7",
0572 "mainpll_d6",
0573 "univpll_d4_d2",
0574 "mainpll_d4_d2",
0575 "univpll_d6",
0576 "mmpll_d6",
0577 "mainpll_d5_d2",
0578 "mainpll_d6_d2",
0579 "mmpll_d9",
0580 "univpll_d4_d4",
0581 "mainpll_d4",
0582 "univpll_d4",
0583 "univpll_d5",
0584 "univpll_d5_d2",
0585 "mainpll_d5"
0586 };
0587
0588 static const char * const vdec_parents[] = {
0589 "clk26m",
0590 "univpll_192m_d2",
0591 "univpll_d5_d4",
0592 "mainpll_d5",
0593 "mainpll_d5_d2",
0594 "mmpll_d6_d2",
0595 "univpll_d5_d2",
0596 "mainpll_d4_d2",
0597 "univpll_d4_d2",
0598 "univpll_d7",
0599 "mmpll_d7",
0600 "mmpll_d6",
0601 "univpll_d5",
0602 "mainpll_d4",
0603 "univpll_d4",
0604 "univpll_d6"
0605 };
0606
0607 static const char * const camtm_parents[] = {
0608 "clk26m",
0609 "univpll_d7",
0610 "univpll_d6_d2",
0611 "univpll_d4_d2"
0612 };
0613
0614 static const char * const pwm_parents[] = {
0615 "clk26m",
0616 "univpll_d4_d8"
0617 };
0618
0619 static const char * const audio_h_parents[] = {
0620 "clk26m",
0621 "univpll_d7",
0622 "apll1_ck",
0623 "apll2_ck"
0624 };
0625
0626 static const char * const spmi_mst_parents[] = {
0627 "clk26m",
0628 "csw_f26m_d2",
0629 "osc_d8",
0630 "osc_d10",
0631 "osc_d16",
0632 "osc_d20",
0633 "clk32k"
0634 };
0635
0636 static const char * const aes_msdcfde_parents[] = {
0637 "clk26m",
0638 "mainpll_d4_d2",
0639 "mainpll_d6",
0640 "mainpll_d4_d4",
0641 "univpll_d4_d2",
0642 "univpll_d6"
0643 };
0644
0645 static const char * const sflash_parents[] = {
0646 "clk26m",
0647 "mainpll_d7_d8",
0648 "univpll_d6_d8",
0649 "univpll_d5_d8"
0650 };
0651
0652 static const char * const apll_i2s0_m_parents[] = {
0653 "aud_1_sel",
0654 "aud_2_sel"
0655 };
0656
0657 static const char * const apll_i2s1_m_parents[] = {
0658 "aud_1_sel",
0659 "aud_2_sel"
0660 };
0661
0662 static const char * const apll_i2s2_m_parents[] = {
0663 "aud_1_sel",
0664 "aud_2_sel"
0665 };
0666
0667 static const char * const apll_i2s3_m_parents[] = {
0668 "aud_1_sel",
0669 "aud_2_sel"
0670 };
0671
0672 static const char * const apll_i2s4_m_parents[] = {
0673 "aud_1_sel",
0674 "aud_2_sel"
0675 };
0676
0677 static const char * const apll_i2s5_m_parents[] = {
0678 "aud_1_sel",
0679 "aud_2_sel"
0680 };
0681
0682 static const char * const apll_i2s6_m_parents[] = {
0683 "aud_1_sel",
0684 "aud_2_sel"
0685 };
0686
0687 static const char * const apll_i2s7_m_parents[] = {
0688 "aud_1_sel",
0689 "aud_2_sel"
0690 };
0691
0692 static const char * const apll_i2s8_m_parents[] = {
0693 "aud_1_sel",
0694 "aud_2_sel"
0695 };
0696
0697 static const char * const apll_i2s9_m_parents[] = {
0698 "aud_1_sel",
0699 "aud_2_sel"
0700 };
0701
0702
0703
0704
0705
0706
0707
0708 static const struct mtk_mux top_mtk_muxes[] = {
0709
0710 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel",
0711 axi_parents, 0x010, 0x014, 0x018, 0, 3, 7, 0x004, 0,
0712 CLK_IS_CRITICAL),
0713 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, "spm_sel",
0714 spm_parents, 0x010, 0x014, 0x018, 8, 2, 15, 0x004, 1,
0715 CLK_IS_CRITICAL),
0716 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel",
0717 scp_parents, 0x010, 0x014, 0x018, 16, 3, 23, 0x004, 2),
0718 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM_SEL, "bus_aximem_sel",
0719 bus_aximem_parents, 0x010, 0x014, 0x018, 24, 3, 31, 0x004, 3,
0720 CLK_IS_CRITICAL),
0721
0722 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_SEL, "disp_sel",
0723 disp_parents, 0x020, 0x024, 0x028, 0, 4, 7, 0x004, 4),
0724 MUX_GATE_CLR_SET_UPD(CLK_TOP_MDP_SEL, "mdp_sel",
0725 mdp_parents, 0x020, 0x024, 0x028, 8, 4, 15, 0x004, 5),
0726 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG1_SEL, "img1_sel",
0727 img1_parents, 0x020, 0x024, 0x028, 16, 4, 23, 0x004, 6),
0728 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG2_SEL, "img2_sel",
0729 img2_parents, 0x020, 0x024, 0x028, 24, 4, 31, 0x004, 7),
0730
0731 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE_SEL, "ipe_sel",
0732 ipe_parents, 0x030, 0x034, 0x038, 0, 4, 7, 0x004, 8),
0733 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE_SEL, "dpe_sel",
0734 dpe_parents, 0x030, 0x034, 0x038, 8, 3, 15, 0x004, 9),
0735 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM_SEL, "cam_sel",
0736 cam_parents, 0x030, 0x034, 0x038, 16, 4, 23, 0x004, 10),
0737 MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU_SEL, "ccu_sel",
0738 ccu_parents, 0x030, 0x034, 0x038, 24, 4, 31, 0x004, 11),
0739
0740 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7_SEL, "dsp7_sel",
0741 dsp7_parents, 0x050, 0x054, 0x058, 0, 3, 7, 0x004, 16),
0742 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_REF_SEL, "mfg_ref_sel",
0743 mfg_ref_parents, 0x050, 0x054, 0x058, 16, 2, 23, 0x004, 18),
0744 MUX_CLR_SET_UPD(CLK_TOP_MFG_PLL_SEL, "mfg_pll_sel",
0745 mfg_pll_parents, 0x050, 0x054, 0x058, 18, 1, -1, -1),
0746 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel",
0747 camtg_parents, 0x050, 0x054, 0x058, 24, 3, 31, 0x004, 19),
0748
0749 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2_SEL, "camtg2_sel",
0750 camtg2_parents, 0x060, 0x064, 0x068, 0, 3, 7, 0x004, 20),
0751 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3_SEL, "camtg3_sel",
0752 camtg3_parents, 0x060, 0x064, 0x068, 8, 3, 15, 0x004, 21),
0753 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4_SEL, "camtg4_sel",
0754 camtg4_parents, 0x060, 0x064, 0x068, 16, 3, 23, 0x004, 22),
0755 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5_SEL, "camtg5_sel",
0756 camtg5_parents, 0x060, 0x064, 0x068, 24, 3, 31, 0x004, 23),
0757
0758 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG6_SEL, "camtg6_sel",
0759 camtg6_parents, 0x070, 0x074, 0x078, 0, 3, 7, 0x004, 24),
0760 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel",
0761 uart_parents, 0x070, 0x074, 0x078, 8, 1, 15, 0x004, 25),
0762 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel",
0763 spi_parents, 0x070, 0x074, 0x078, 16, 2, 23, 0x004, 26),
0764 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel",
0765 msdc50_0_h_parents, 0x070, 0x074, 0x078, 24, 2, 31, 0x004, 27),
0766
0767 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
0768 msdc50_0_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x004, 28),
0769 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
0770 msdc30_1_parents, 0x080, 0x084, 0x088, 8, 3, 15, 0x004, 29),
0771 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel",
0772 msdc30_2_parents, 0x080, 0x084, 0x088, 16, 3, 23, 0x004, 30),
0773 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel",
0774 audio_parents, 0x080, 0x084, 0x088, 24, 2, 31, 0x008, 0),
0775
0776 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
0777 aud_intbus_parents, 0x090, 0x094, 0x098, 0, 2, 7, 0x008, 1),
0778 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC_SEL, "pwrap_ulposc_sel",
0779 pwrap_ulposc_parents, 0x090, 0x094, 0x098, 8, 3, 15, 0x008, 2),
0780 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel",
0781 atb_parents, 0x090, 0x094, 0x098, 16, 2, 23, 0x008, 3),
0782
0783 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI_SEL, "dpi_sel",
0784 dpi_parents, 0x0a0, 0x0a4, 0x0a8, 0, 3, 7, 0x008, 5),
0785 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCAM_SEL, "scam_sel",
0786 scam_parents, 0x0a0, 0x0a4, 0x0a8, 8, 1, 15, 0x008, 6),
0787 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel",
0788 disp_pwm_parents, 0x0a0, 0x0a4, 0x0a8, 16, 3, 23, 0x008, 7),
0789 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_SEL, "usb_top_sel",
0790 usb_top_parents, 0x0a0, 0x0a4, 0x0a8, 24, 2, 31, 0x008, 8),
0791
0792 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_SEL, "ssusb_xhci_sel",
0793 ssusb_xhci_parents, 0x0b0, 0x0b4, 0x0b8, 0, 2, 7, 0x008, 9),
0794 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel",
0795 i2c_parents, 0x0b0, 0x0b4, 0x0b8, 8, 2, 15, 0x008, 10),
0796 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, "seninf_sel",
0797 seninf_parents, 0x0b0, 0x0b4, 0x0b8, 16, 3, 23, 0x008, 11),
0798 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1_SEL, "seninf1_sel",
0799 seninf1_parents, 0x0b0, 0x0b4, 0x0b8, 24, 3, 31, 0x008, 12),
0800
0801 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2_SEL, "seninf2_sel",
0802 seninf2_parents, 0x0c0, 0x0c4, 0x0c8, 0, 3, 7, 0x008, 13),
0803 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF3_SEL, "seninf3_sel",
0804 seninf3_parents, 0x0c0, 0x0c4, 0x0c8, 8, 3, 15, 0x008, 14),
0805 MUX_GATE_CLR_SET_UPD(CLK_TOP_TL_SEL, "tl_sel",
0806 tl_parents, 0x0c0, 0x0c4, 0x0c8, 16, 2, 23, 0x008, 15),
0807 MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, "dxcc_sel",
0808 dxcc_parents, 0x0c0, 0x0c4, 0x0c8, 24, 2, 31, 0x008, 16),
0809
0810 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel",
0811 aud_engen1_parents, 0x0d0, 0x0d4, 0x0d8, 0, 2, 7, 0x008, 17),
0812 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel",
0813 aud_engen2_parents, 0x0d0, 0x0d4, 0x0d8, 8, 2, 15, 0x008, 18),
0814 MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_UFSFDE_SEL, "aes_ufsfde_sel",
0815 aes_ufsfde_parents, 0x0d0, 0x0d4, 0x0d8, 16, 3, 23, 0x008, 19),
0816 MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_SEL, "ufs_sel",
0817 ufs_parents, 0x0d0, 0x0d4, 0x0d8, 24, 3, 31, 0x008, 20),
0818
0819 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel",
0820 aud_1_parents, 0x0e0, 0x0e4, 0x0e8, 0, 1, 7, 0x008, 21),
0821 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, "aud_2_sel",
0822 aud_2_parents, 0x0e0, 0x0e4, 0x0e8, 8, 1, 15, 0x008, 22),
0823 MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP_SEL, "adsp_sel",
0824 adsp_parents, 0x0e0, 0x0e4, 0x0e8, 16, 3, 23, 0x008, 23),
0825 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF_MAIN_SEL, "dpmaif_main_sel",
0826 dpmaif_main_parents, 0x0e0, 0x0e4, 0x0e8, 24, 3, 31, 0x008, 24),
0827
0828 MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC_SEL, "venc_sel",
0829 venc_parents, 0x0f0, 0x0f4, 0x0f8, 0, 4, 7, 0x008, 25),
0830 MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC_SEL, "vdec_sel",
0831 vdec_parents, 0x0f0, 0x0f4, 0x0f8, 8, 4, 15, 0x008, 26),
0832 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel",
0833 camtm_parents, 0x0f0, 0x0f4, 0x0f8, 16, 2, 23, 0x008, 27),
0834 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel",
0835 pwm_parents, 0x0f0, 0x0f4, 0x0f8, 24, 1, 31, 0x008, 28),
0836
0837 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H_SEL, "audio_h_sel",
0838 audio_h_parents, 0x100, 0x104, 0x108, 0, 2, 7, 0x008, 29),
0839 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_MST_SEL, "spmi_mst_sel",
0840 spmi_mst_parents, 0x100, 0x104, 0x108, 8, 3, 15, 0x008, 30),
0841 MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE_SEL, "aes_msdcfde_sel",
0842 aes_msdcfde_parents, 0x100, 0x104, 0x108, 24, 3, 31, 0x00c, 1),
0843
0844 MUX_GATE_CLR_SET_UPD(CLK_TOP_SFLASH_SEL, "sflash_sel",
0845 sflash_parents, 0x110, 0x114, 0x118, 8, 2, 15, 0x00c, 3),
0846 };
0847
0848 static struct mtk_composite top_muxes[] = {
0849
0850 MUX(CLK_TOP_APLL_I2S0_M_SEL, "apll_i2s0_m_sel", apll_i2s0_m_parents, 0x320, 16, 1),
0851 MUX(CLK_TOP_APLL_I2S1_M_SEL, "apll_i2s1_m_sel", apll_i2s1_m_parents, 0x320, 17, 1),
0852 MUX(CLK_TOP_APLL_I2S2_M_SEL, "apll_i2s2_m_sel", apll_i2s2_m_parents, 0x320, 18, 1),
0853 MUX(CLK_TOP_APLL_I2S3_M_SEL, "apll_i2s3_m_sel", apll_i2s3_m_parents, 0x320, 19, 1),
0854 MUX(CLK_TOP_APLL_I2S4_M_SEL, "apll_i2s4_m_sel", apll_i2s4_m_parents, 0x320, 20, 1),
0855 MUX(CLK_TOP_APLL_I2S5_M_SEL, "apll_i2s5_m_sel", apll_i2s5_m_parents, 0x320, 21, 1),
0856 MUX(CLK_TOP_APLL_I2S6_M_SEL, "apll_i2s6_m_sel", apll_i2s6_m_parents, 0x320, 22, 1),
0857 MUX(CLK_TOP_APLL_I2S7_M_SEL, "apll_i2s7_m_sel", apll_i2s7_m_parents, 0x320, 23, 1),
0858 MUX(CLK_TOP_APLL_I2S8_M_SEL, "apll_i2s8_m_sel", apll_i2s8_m_parents, 0x320, 24, 1),
0859 MUX(CLK_TOP_APLL_I2S9_M_SEL, "apll_i2s9_m_sel", apll_i2s9_m_parents, 0x320, 25, 1),
0860 };
0861
0862 static const struct mtk_composite top_adj_divs[] = {
0863 DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_m_sel", 0x320, 0, 0x328, 8, 0),
0864 DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_m_sel", 0x320, 1, 0x328, 8, 8),
0865 DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_m_sel", 0x320, 2, 0x328, 8, 16),
0866 DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_m_sel", 0x320, 3, 0x328, 8, 24),
0867 DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_m_sel", 0x320, 4, 0x334, 8, 0),
0868 DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4", 0x320, 5, 0x334, 8, 8),
0869 DIV_GATE(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll_i2s5_m_sel", 0x320, 6, 0x334, 8, 16),
0870 DIV_GATE(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll_i2s6_m_sel", 0x320, 7, 0x334, 8, 24),
0871 DIV_GATE(CLK_TOP_APLL12_DIV7, "apll12_div7", "apll_i2s7_m_sel", 0x320, 8, 0x338, 8, 0),
0872 DIV_GATE(CLK_TOP_APLL12_DIV8, "apll12_div8", "apll_i2s8_m_sel", 0x320, 9, 0x338, 8, 8),
0873 DIV_GATE(CLK_TOP_APLL12_DIV9, "apll12_div9", "apll_i2s9_m_sel", 0x320, 10, 0x338, 8, 16),
0874 };
0875
0876 static const struct mtk_gate_regs apmixed_cg_regs = {
0877 .set_ofs = 0x14,
0878 .clr_ofs = 0x14,
0879 .sta_ofs = 0x14,
0880 };
0881
0882 #define GATE_APMIXED(_id, _name, _parent, _shift) \
0883 GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
0884
0885 static const struct mtk_gate apmixed_clks[] = {
0886 GATE_APMIXED(CLK_APMIXED_MIPID26M, "mipid26m", "clk26m", 16),
0887 };
0888
0889 static const struct mtk_gate_regs infra0_cg_regs = {
0890 .set_ofs = 0x80,
0891 .clr_ofs = 0x84,
0892 .sta_ofs = 0x90,
0893 };
0894
0895 static const struct mtk_gate_regs infra1_cg_regs = {
0896 .set_ofs = 0x88,
0897 .clr_ofs = 0x8c,
0898 .sta_ofs = 0x94,
0899 };
0900
0901 static const struct mtk_gate_regs infra2_cg_regs = {
0902 .set_ofs = 0xa4,
0903 .clr_ofs = 0xa8,
0904 .sta_ofs = 0xac,
0905 };
0906
0907 static const struct mtk_gate_regs infra3_cg_regs = {
0908 .set_ofs = 0xc0,
0909 .clr_ofs = 0xc4,
0910 .sta_ofs = 0xc8,
0911 };
0912
0913 static const struct mtk_gate_regs infra4_cg_regs = {
0914 .set_ofs = 0xd0,
0915 .clr_ofs = 0xd4,
0916 .sta_ofs = 0xd8,
0917 };
0918
0919 static const struct mtk_gate_regs infra5_cg_regs = {
0920 .set_ofs = 0xe0,
0921 .clr_ofs = 0xe4,
0922 .sta_ofs = 0xe8,
0923 };
0924
0925 #define GATE_INFRA0(_id, _name, _parent, _shift) \
0926 GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
0927
0928 #define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flag) \
0929 GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, \
0930 &mtk_clk_gate_ops_setclr, _flag)
0931
0932 #define GATE_INFRA1(_id, _name, _parent, _shift) \
0933 GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0)
0934
0935 #define GATE_INFRA2(_id, _name, _parent, _shift) \
0936 GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
0937
0938 #define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flag) \
0939 GATE_MTK_FLAGS(_id, _name, _parent, &infra3_cg_regs, _shift, \
0940 &mtk_clk_gate_ops_setclr, _flag)
0941
0942 #define GATE_INFRA3(_id, _name, _parent, _shift) \
0943 GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0)
0944
0945 #define GATE_INFRA4(_id, _name, _parent, _shift) \
0946 GATE_MTK(_id, _name, _parent, &infra4_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
0947
0948 #define GATE_INFRA5_FLAGS(_id, _name, _parent, _shift, _flag) \
0949 GATE_MTK_FLAGS(_id, _name, _parent, &infra5_cg_regs, _shift, \
0950 &mtk_clk_gate_ops_setclr, _flag)
0951
0952 #define GATE_INFRA5(_id, _name, _parent, _shift) \
0953 GATE_INFRA5_FLAGS(_id, _name, _parent, _shift, 0)
0954
0955
0956
0957
0958
0959
0960 static const struct mtk_gate infra_clks[] = {
0961
0962 GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "pwrap_ulposc_sel", 0),
0963 GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "pwrap_ulposc_sel", 1),
0964 GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md", "pwrap_ulposc_sel", 2),
0965 GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", "pwrap_ulposc_sel", 3),
0966 GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scpsys", "scp_sel", 4),
0967 GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", "axi_sel", 5),
0968 GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6),
0969 GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 8),
0970 GATE_INFRA0(CLK_INFRA_GCE2, "infra_gce2", "axi_sel", 9),
0971 GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10),
0972 GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0", "i2c_sel", 11),
0973 GATE_INFRA0(CLK_INFRA_AP_DMA_PSEUDO, "infra_ap_dma_pseudo", "axi_sel", 12),
0974 GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2", "i2c_sel", 13),
0975 GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3", "i2c_sel", 14),
0976 GATE_INFRA0(CLK_INFRA_PWM_H, "infra_pwm_h", "axi_sel", 15),
0977 GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1", "pwm_sel", 16),
0978 GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2", "pwm_sel", 17),
0979 GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3", "pwm_sel", 18),
0980 GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4", "pwm_sel", 19),
0981 GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", "pwm_sel", 21),
0982 GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22),
0983 GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23),
0984 GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24),
0985 GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25),
0986 GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m", "axi_sel", 27),
0987 GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cq_dma_fpc", "axi_sel", 28),
0988 GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif", "axi_sel", 31),
0989
0990 GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0", "spi_sel", 1),
0991 GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0", "msdc50_0_h_sel", 2),
0992 GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1", "msdc50_0_h_sel", 4),
0993 GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2", "msdc50_0_h_sel", 5),
0994 GATE_INFRA1(CLK_INFRA_MSDC0_SRC, "infra_msdc0_src", "msdc50_0_sel", 6),
0995 GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu", "axi_sel", 8),
0996 GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 9),
0997 GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc", "clk26m", 10),
0998 GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum", "axi_sel", 11),
0999 GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap", "axi_sel", 12),
1000 GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md", "axi_sel", 13),
1001 GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md", "clk26m", 14),
1002 GATE_INFRA1(CLK_INFRA_PCIE_TL_26M, "infra_pcie_tl_26m", "axi_sel", 15),
1003 GATE_INFRA1(CLK_INFRA_MSDC1_SRC, "infra_msdc1_src", "msdc30_1_sel", 16),
1004 GATE_INFRA1(CLK_INFRA_MSDC2_SRC, "infra_msdc2_src", "msdc30_2_sel", 17),
1005 GATE_INFRA1(CLK_INFRA_PCIE_TL_96M, "infra_pcie_tl_96m", "tl_sel", 18),
1006 GATE_INFRA1(CLK_INFRA_PCIE_PL_P_250M, "infra_pcie_pl_p_250m", "axi_sel", 19),
1007 GATE_INFRA1_FLAGS(CLK_INFRA_DEVICE_APC, "infra_device_apc", "axi_sel", 20, CLK_IS_CRITICAL),
1008 GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23),
1009 GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys", "axi_sel", 24),
1010 GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25),
1011 GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26),
1012 GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core", "dxcc_sel", 27),
1013 GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao", "dxcc_sel", 28),
1014 GATE_INFRA1(CLK_INFRA_DBG_TRACE, "infra_dbg_trace", "axi_sel", 29),
1015 GATE_INFRA1(CLK_INFRA_DEVMPU_B, "infra_devmpu_b", "axi_sel", 30),
1016 GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "clk26m", 31),
1017
1018 GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx", "clk26m", 0),
1019 GATE_INFRA2(CLK_INFRA_SSUSB, "infra_ssusb", "usb_top_sel", 1),
1020 GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disp_pwm", "axi_sel", 2),
1021 GATE_INFRA2(CLK_INFRA_CLDMA_B, "infra_cldma_b", "axi_sel", 3),
1022 GATE_INFRA2(CLK_INFRA_AUDIO_26M_B, "infra_audio_26m_b", "clk26m", 4),
1023 GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_modem_temp_share", "clk26m", 5),
1024 GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 6),
1025 GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4", "i2c_sel", 7),
1026 GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2", "spi_sel", 9),
1027 GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3", "spi_sel", 10),
1028 GATE_INFRA2(CLK_INFRA_UNIPRO_SYS, "infra_unipro_sys", "ufs_sel", 11),
1029 GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick", "clk26m", 12),
1030 GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_B, "infra_ufs_mp_sap_b", "clk26m", 13),
1031 GATE_INFRA2(CLK_INFRA_MD32_B, "infra_md32_b", "axi_sel", 14),
1032 GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", "axi_sel", 16),
1033 GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5", "i2c_sel", 18),
1034 GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter", "i2c_sel", 19),
1035 GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm", "i2c_sel", 20),
1036 GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter", "i2c_sel", 21),
1037 GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm", "i2c_sel", 22),
1038 GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter", "i2c_sel", 23),
1039 GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", "i2c_sel", 24),
1040 GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4", "spi_sel", 25),
1041 GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5", "spi_sel", 26),
1042 GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cq_dma", "axi_sel", 27),
1043 GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs", "ufs_sel", 28),
1044 GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde", "aes_ufsfde_sel", 29),
1045 GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick", "ufs_sel", 30),
1046 GATE_INFRA2(CLK_INFRA_SSUSB_XHCI, "infra_ssusb_xhci", "ssusb_xhci_sel", 31),
1047
1048 GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self", "msdc50_0_sel", 0),
1049 GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self", "msdc50_0_sel", 1),
1050 GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self", "msdc50_0_sel", 2),
1051 GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi", "axi_sel", 5),
1052 GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6", "i2c_sel", 6),
1053 GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0", "msdc50_0_sel", 7),
1054 GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0", "msdc50_0_sel", 8),
1055 GATE_INFRA3(CLK_INFRA_CCIF5_AP, "infra_ccif5_ap", "axi_sel", 9),
1056 GATE_INFRA3(CLK_INFRA_CCIF5_MD, "infra_ccif5_md", "axi_sel", 10),
1057 GATE_INFRA3(CLK_INFRA_PCIE_TOP_H_133M, "infra_pcie_top_h_133m", "axi_sel", 11),
1058 GATE_INFRA3(CLK_INFRA_FLASHIF_TOP_H_133M, "infra_flashif_top_h_133m", "axi_sel", 14),
1059 GATE_INFRA3(CLK_INFRA_PCIE_PERI_26M, "infra_pcie_peri_26m", "axi_sel", 15),
1060 GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap", "axi_sel", 16),
1061 GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md", "axi_sel", 17),
1062 GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap", "axi_sel", 18),
1063 GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md", "axi_sel", 19),
1064 GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m", "clk26m", 20),
1065 GATE_INFRA3(CLK_INFRA_AES, "infra_aes", "axi_sel", 21),
1066 GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7", "i2c_sel", 22),
1067 GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8", "i2c_sel", 23),
1068 GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc", "msdc50_0_sel", 24),
1069 GATE_INFRA3_FLAGS(CLK_INFRA_DEVICE_APC_SYNC, "infra_device_apc_sync", "axi_sel", 25,
1070 CLK_IS_CRITICAL),
1071 GATE_INFRA3(CLK_INFRA_DPMAIF_MAIN, "infra_dpmaif_main", "dpmaif_main_sel", 26),
1072 GATE_INFRA3(CLK_INFRA_PCIE_TL_32K, "infra_pcie_tl_32k", "axi_sel", 27),
1073 GATE_INFRA3(CLK_INFRA_CCIF4_AP, "infra_ccif4_ap", "axi_sel", 28),
1074 GATE_INFRA3(CLK_INFRA_CCIF4_MD, "infra_ccif4_md", "axi_sel", 29),
1075 GATE_INFRA3(CLK_INFRA_SPI6, "infra_spi6", "spi_sel", 30),
1076 GATE_INFRA3(CLK_INFRA_SPI7, "infra_spi7", "spi_sel", 31),
1077
1078 GATE_INFRA4(CLK_INFRA_AP_DMA, "infra_ap_dma", "infra_ap_dma_pseudo", 31),
1079
1080 GATE_INFRA5_FLAGS(CLK_INFRA_133M, "infra_133m", "axi_sel", 0, CLK_IS_CRITICAL),
1081 GATE_INFRA5_FLAGS(CLK_INFRA_66M, "infra_66m", "axi_sel", 1, CLK_IS_CRITICAL),
1082 GATE_INFRA5(CLK_INFRA_66M_PERI_BUS, "infra_66m_peri_bus", "axi_sel", 2),
1083 GATE_INFRA5(CLK_INFRA_FREE_DCM_133M, "infra_free_dcm_133m", "axi_sel", 3),
1084 GATE_INFRA5(CLK_INFRA_FREE_DCM_66M, "infra_free_dcm_66m", "axi_sel", 4),
1085 GATE_INFRA5(CLK_INFRA_PERI_BUS_DCM_133M, "infra_peri_bus_dcm_133m", "axi_sel", 5),
1086 GATE_INFRA5(CLK_INFRA_PERI_BUS_DCM_66M, "infra_peri_bus_dcm_66m", "axi_sel", 6),
1087 GATE_INFRA5(CLK_INFRA_FLASHIF_PERI_26M, "infra_flashif_peri_26m", "axi_sel", 30),
1088 GATE_INFRA5(CLK_INFRA_FLASHIF_SFLASH, "infra_flashif_fsflash", "axi_sel", 31),
1089 };
1090
1091 static const struct mtk_gate_regs peri_cg_regs = {
1092 .set_ofs = 0x20c,
1093 .clr_ofs = 0x20c,
1094 .sta_ofs = 0x20c,
1095 };
1096
1097 #define GATE_PERI(_id, _name, _parent, _shift) \
1098 GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
1099
1100 static const struct mtk_gate peri_clks[] = {
1101 GATE_PERI(CLK_PERI_PERIAXI, "peri_periaxi", "axi_sel", 31),
1102 };
1103
1104 static const struct mtk_gate_regs top_cg_regs = {
1105 .set_ofs = 0x150,
1106 .clr_ofs = 0x150,
1107 .sta_ofs = 0x150,
1108 };
1109
1110 #define GATE_TOP(_id, _name, _parent, _shift) \
1111 GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
1112
1113 static const struct mtk_gate top_clks[] = {
1114 GATE_TOP(CLK_TOP_SSUSB_TOP_REF, "ssusb_top_ref", "clk26m", 24),
1115 GATE_TOP(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 25),
1116 };
1117
1118 static u16 infra_ao_rst_ofs[] = {
1119 INFRA_RST0_SET_OFFSET,
1120 INFRA_RST1_SET_OFFSET,
1121 INFRA_RST2_SET_OFFSET,
1122 INFRA_RST3_SET_OFFSET,
1123 INFRA_RST4_SET_OFFSET,
1124 };
1125
1126 static u16 infra_ao_idx_map[] = {
1127 [MT8192_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0,
1128 [MT8192_INFRA_RST2_PEXTP_PHY_SWRST] = 2 * RST_NR_PER_BANK + 15,
1129 [MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5,
1130 [MT8192_INFRA_RST4_PCIE_TOP_SWRST] = 4 * RST_NR_PER_BANK + 1,
1131 [MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 12,
1132 };
1133
1134 static const struct mtk_clk_rst_desc clk_rst_desc = {
1135 .version = MTK_RST_SET_CLR,
1136 .rst_bank_ofs = infra_ao_rst_ofs,
1137 .rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),
1138 .rst_idx_map = infra_ao_idx_map,
1139 .rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),
1140 };
1141
1142 #define MT8192_PLL_FMAX (3800UL * MHZ)
1143 #define MT8192_PLL_FMIN (1500UL * MHZ)
1144 #define MT8192_INTEGER_BITS 8
1145
1146 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1147 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
1148 _tuner_reg, _tuner_en_reg, _tuner_en_bit, \
1149 _pcw_reg, _pcw_shift, _pcw_chg_reg, \
1150 _en_reg, _pll_en_bit) { \
1151 .id = _id, \
1152 .name = _name, \
1153 .reg = _reg, \
1154 .pwr_reg = _pwr_reg, \
1155 .en_mask = _en_mask, \
1156 .flags = _flags, \
1157 .rst_bar_mask = _rst_bar_mask, \
1158 .fmax = MT8192_PLL_FMAX, \
1159 .fmin = MT8192_PLL_FMIN, \
1160 .pcwbits = _pcwbits, \
1161 .pcwibits = MT8192_INTEGER_BITS, \
1162 .pd_reg = _pd_reg, \
1163 .pd_shift = _pd_shift, \
1164 .tuner_reg = _tuner_reg, \
1165 .tuner_en_reg = _tuner_en_reg, \
1166 .tuner_en_bit = _tuner_en_bit, \
1167 .pcw_reg = _pcw_reg, \
1168 .pcw_shift = _pcw_shift, \
1169 .pcw_chg_reg = _pcw_chg_reg, \
1170 .en_reg = _en_reg, \
1171 .pll_en_bit = _pll_en_bit, \
1172 }
1173
1174 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1175 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
1176 _tuner_reg, _tuner_en_reg, _tuner_en_bit, \
1177 _pcw_reg, _pcw_shift) \
1178 PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1179 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
1180 _tuner_reg, _tuner_en_reg, _tuner_en_bit, \
1181 _pcw_reg, _pcw_shift, 0, 0, 0)
1182
1183 static const struct mtk_pll_data plls[] = {
1184 PLL_B(CLK_APMIXED_MAINPLL, "mainpll", 0x0340, 0x034c, 0xff000000,
1185 HAVE_RST_BAR, BIT(23), 22, 0x0344, 24, 0, 0, 0, 0x0344, 0),
1186 PLL_B(CLK_APMIXED_UNIVPLL, "univpll", 0x0308, 0x0314, 0xff000000,
1187 HAVE_RST_BAR, BIT(23), 22, 0x030c, 24, 0, 0, 0, 0x030c, 0),
1188 PLL(CLK_APMIXED_USBPLL, "usbpll", 0x03c4, 0x03cc, 0x00000000,
1189 0, 0, 22, 0x03c4, 24, 0, 0, 0, 0x03c4, 0, 0x03c4, 0x03cc, 2),
1190 PLL_B(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0350, 0x035c, 0x00000000,
1191 0, 0, 22, 0x0354, 24, 0, 0, 0, 0x0354, 0),
1192 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0360, 0x036c, 0xff000000,
1193 HAVE_RST_BAR, BIT(23), 22, 0x0364, 24, 0, 0, 0, 0x0364, 0),
1194 PLL_B(CLK_APMIXED_ADSPPLL, "adsppll", 0x0370, 0x037c, 0xff000000,
1195 HAVE_RST_BAR, BIT(23), 22, 0x0374, 24, 0, 0, 0, 0x0374, 0),
1196 PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0268, 0x0274, 0x00000000,
1197 0, 0, 22, 0x026c, 24, 0, 0, 0, 0x026c, 0),
1198 PLL_B(CLK_APMIXED_TVDPLL, "tvdpll", 0x0380, 0x038c, 0x00000000,
1199 0, 0, 22, 0x0384, 24, 0, 0, 0, 0x0384, 0),
1200 PLL_B(CLK_APMIXED_APLL1, "apll1", 0x0318, 0x0328, 0x00000000,
1201 0, 0, 32, 0x031c, 24, 0x0040, 0x000c, 0, 0x0320, 0),
1202 PLL_B(CLK_APMIXED_APLL2, "apll2", 0x032c, 0x033c, 0x00000000,
1203 0, 0, 32, 0x0330, 24, 0, 0, 0, 0x0334, 0),
1204 };
1205
1206 static struct clk_hw_onecell_data *top_clk_data;
1207
1208 static void clk_mt8192_top_init_early(struct device_node *node)
1209 {
1210 int i;
1211
1212 top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1213 if (!top_clk_data)
1214 return;
1215
1216 for (i = 0; i < CLK_TOP_NR_CLK; i++)
1217 top_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
1218
1219 mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), top_clk_data);
1220
1221 of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
1222 }
1223
1224 CLK_OF_DECLARE_DRIVER(mt8192_topckgen, "mediatek,mt8192-topckgen",
1225 clk_mt8192_top_init_early);
1226
1227 static int clk_mt8192_top_probe(struct platform_device *pdev)
1228 {
1229 struct device_node *node = pdev->dev.of_node;
1230 int r;
1231 void __iomem *base;
1232
1233 base = devm_platform_ioremap_resource(pdev, 0);
1234 if (IS_ERR(base))
1235 return PTR_ERR(base);
1236
1237 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data);
1238 mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), top_clk_data);
1239 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
1240 mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), node, &mt8192_clk_lock,
1241 top_clk_data);
1242 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, &mt8192_clk_lock,
1243 top_clk_data);
1244 mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, &mt8192_clk_lock,
1245 top_clk_data);
1246 r = mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_clk_data);
1247 if (r)
1248 return r;
1249
1250 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
1251 top_clk_data);
1252 }
1253
1254 static int clk_mt8192_infra_probe(struct platform_device *pdev)
1255 {
1256 struct clk_hw_onecell_data *clk_data;
1257 struct device_node *node = pdev->dev.of_node;
1258 int r;
1259
1260 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
1261 if (!clk_data)
1262 return -ENOMEM;
1263
1264 r = mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), clk_data);
1265 if (r)
1266 goto free_clk_data;
1267
1268 r = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
1269 if (r)
1270 goto free_clk_data;
1271
1272 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1273 if (r)
1274 goto free_clk_data;
1275
1276 return r;
1277
1278 free_clk_data:
1279 mtk_free_clk_data(clk_data);
1280 return r;
1281 }
1282
1283 static int clk_mt8192_peri_probe(struct platform_device *pdev)
1284 {
1285 struct clk_hw_onecell_data *clk_data;
1286 struct device_node *node = pdev->dev.of_node;
1287 int r;
1288
1289 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
1290 if (!clk_data)
1291 return -ENOMEM;
1292
1293 r = mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), clk_data);
1294 if (r)
1295 goto free_clk_data;
1296
1297 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1298 if (r)
1299 goto free_clk_data;
1300
1301 return r;
1302
1303 free_clk_data:
1304 mtk_free_clk_data(clk_data);
1305 return r;
1306 }
1307
1308 static int clk_mt8192_apmixed_probe(struct platform_device *pdev)
1309 {
1310 struct clk_hw_onecell_data *clk_data;
1311 struct device_node *node = pdev->dev.of_node;
1312 int r;
1313
1314 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
1315 if (!clk_data)
1316 return -ENOMEM;
1317
1318 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
1319 r = mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
1320 if (r)
1321 goto free_clk_data;
1322
1323 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1324 if (r)
1325 goto free_clk_data;
1326
1327 return r;
1328
1329 free_clk_data:
1330 mtk_free_clk_data(clk_data);
1331 return r;
1332 }
1333
1334 static const struct of_device_id of_match_clk_mt8192[] = {
1335 {
1336 .compatible = "mediatek,mt8192-apmixedsys",
1337 .data = clk_mt8192_apmixed_probe,
1338 }, {
1339 .compatible = "mediatek,mt8192-topckgen",
1340 .data = clk_mt8192_top_probe,
1341 }, {
1342 .compatible = "mediatek,mt8192-infracfg",
1343 .data = clk_mt8192_infra_probe,
1344 }, {
1345 .compatible = "mediatek,mt8192-pericfg",
1346 .data = clk_mt8192_peri_probe,
1347 }, {
1348
1349 }
1350 };
1351
1352 static int clk_mt8192_probe(struct platform_device *pdev)
1353 {
1354 int (*clk_probe)(struct platform_device *pdev);
1355 int r;
1356
1357 clk_probe = of_device_get_match_data(&pdev->dev);
1358 if (!clk_probe)
1359 return -EINVAL;
1360
1361 r = clk_probe(pdev);
1362 if (r)
1363 dev_err(&pdev->dev, "could not register clock provider: %s: %d\n", pdev->name, r);
1364
1365 return r;
1366 }
1367
1368 static struct platform_driver clk_mt8192_drv = {
1369 .probe = clk_mt8192_probe,
1370 .driver = {
1371 .name = "clk-mt8192",
1372 .of_match_table = of_match_clk_mt8192,
1373 },
1374 };
1375
1376 static int __init clk_mt8192_init(void)
1377 {
1378 return platform_driver_register(&clk_mt8192_drv);
1379 }
1380
1381 arch_initcall(clk_mt8192_init);
