clk/mediatek/clk-mt8192-venc.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // Copyright (c) 2021 MediaTek Inc.
0004 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
0005
0006 #include <linux/clk-provider.h>
0007 #include <linux/of_device.h>
0008 #include <linux/platform_device.h>
0009
0010 #include "clk-mtk.h"
0011 #include "clk-gate.h"
0012
0013 #include <dt-bindings/clock/mt8192-clk.h>
0014
0015 static const struct mtk_gate_regs venc_cg_regs = {
0016     .set_ofs = 0x4,
0017     .clr_ofs = 0x8,
0018     .sta_ofs = 0x0,
0019 };
0020
0021 #define GATE_VENC(_id, _name, _parent, _shift)  \
0022     GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
0023
0024 static const struct mtk_gate venc_clks[] = {
0025     GATE_VENC(CLK_VENC_SET0_LARB, "venc_set0_larb", "venc_sel", 0),
0026     GATE_VENC(CLK_VENC_SET1_VENC, "venc_set1_venc", "venc_sel", 4),
0027     GATE_VENC(CLK_VENC_SET2_JPGENC, "venc_set2_jpgenc", "venc_sel", 8),
0028     GATE_VENC(CLK_VENC_SET5_GALS, "venc_set5_gals", "venc_sel", 28),
0029 };
0030
0031 static const struct mtk_clk_desc venc_desc = {
0032     .clks = venc_clks,
0033     .num_clks = ARRAY_SIZE(venc_clks),
0034 };
0035
0036 static const struct of_device_id of_match_clk_mt8192_venc[] = {
0037     {
0038         .compatible = "mediatek,mt8192-vencsys",
0039         .data = &venc_desc,
0040     }, {
0041         /* sentinel */
0042     }
0043 };
0044
0045 static struct platform_driver clk_mt8192_venc_drv = {
0046     .probe = mtk_clk_simple_probe,
0047     .driver = {
0048         .name = "clk-mt8192-venc",
0049         .of_match_table = of_match_clk_mt8192_venc,
0050     },
0051 };
0052
0053 builtin_platform_driver(clk_mt8192_venc_drv);