clk/mediatek/clk-mt8192-vdec.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // Copyright (c) 2021 MediaTek Inc.
0004 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
0005
0006 #include <linux/clk-provider.h>
0007 #include <linux/of_device.h>
0008 #include <linux/platform_device.h>
0009
0010 #include "clk-mtk.h"
0011 #include "clk-gate.h"
0012
0013 #include <dt-bindings/clock/mt8192-clk.h>
0014
0015 static const struct mtk_gate_regs vdec0_cg_regs = {
0016     .set_ofs = 0x0,
0017     .clr_ofs = 0x4,
0018     .sta_ofs = 0x0,
0019 };
0020
0021 static const struct mtk_gate_regs vdec1_cg_regs = {
0022     .set_ofs = 0x200,
0023     .clr_ofs = 0x204,
0024     .sta_ofs = 0x200,
0025 };
0026
0027 static const struct mtk_gate_regs vdec2_cg_regs = {
0028     .set_ofs = 0x8,
0029     .clr_ofs = 0xc,
0030     .sta_ofs = 0x8,
0031 };
0032
0033 #define GATE_VDEC0(_id, _name, _parent, _shift) \
0034     GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
0035
0036 #define GATE_VDEC1(_id, _name, _parent, _shift) \
0037     GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
0038
0039 #define GATE_VDEC2(_id, _name, _parent, _shift) \
0040     GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
0041
0042 static const struct mtk_gate vdec_clks[] = {
0043     /* VDEC0 */
0044     GATE_VDEC0(CLK_VDEC_VDEC, "vdec_vdec", "vdec_sel", 0),
0045     GATE_VDEC0(CLK_VDEC_ACTIVE, "vdec_active", "vdec_sel", 4),
0046     /* VDEC1 */
0047     GATE_VDEC1(CLK_VDEC_LAT, "vdec_lat", "vdec_sel", 0),
0048     GATE_VDEC1(CLK_VDEC_LAT_ACTIVE, "vdec_lat_active", "vdec_sel", 4),
0049     /* VDEC2 */
0050     GATE_VDEC2(CLK_VDEC_LARB1, "vdec_larb1", "vdec_sel", 0),
0051 };
0052
0053 static const struct mtk_gate vdec_soc_clks[] = {
0054     /* VDEC_SOC0 */
0055     GATE_VDEC0(CLK_VDEC_SOC_VDEC, "vdec_soc_vdec", "vdec_sel", 0),
0056     GATE_VDEC0(CLK_VDEC_SOC_VDEC_ACTIVE, "vdec_soc_vdec_active", "vdec_sel", 4),
0057     /* VDEC_SOC1 */
0058     GATE_VDEC1(CLK_VDEC_SOC_LAT, "vdec_soc_lat", "vdec_sel", 0),
0059     GATE_VDEC1(CLK_VDEC_SOC_LAT_ACTIVE, "vdec_soc_lat_active", "vdec_sel", 4),
0060     /* VDEC_SOC2 */
0061     GATE_VDEC2(CLK_VDEC_SOC_LARB1, "vdec_soc_larb1", "vdec_sel", 0),
0062 };
0063
0064 static const struct mtk_clk_desc vdec_desc = {
0065     .clks = vdec_clks,
0066     .num_clks = ARRAY_SIZE(vdec_clks),
0067 };
0068
0069 static const struct mtk_clk_desc vdec_soc_desc = {
0070     .clks = vdec_soc_clks,
0071     .num_clks = ARRAY_SIZE(vdec_soc_clks),
0072 };
0073
0074 static const struct of_device_id of_match_clk_mt8192_vdec[] = {
0075     {
0076         .compatible = "mediatek,mt8192-vdecsys",
0077         .data = &vdec_desc,
0078     }, {
0079         .compatible = "mediatek,mt8192-vdecsys_soc",
0080         .data = &vdec_soc_desc,
0081     }, {
0082         /* sentinel */
0083     }
0084 };
0085
0086 static struct platform_driver clk_mt8192_vdec_drv = {
0087     .probe = mtk_clk_simple_probe,
0088     .driver = {
0089         .name = "clk-mt8192-vdec",
0090         .of_match_table = of_match_clk_mt8192_vdec,
0091     },
0092 };
0093
0094 builtin_platform_driver(clk_mt8192_vdec_drv);