clk/mediatek/clk-mt8192-mm.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // Copyright (c) 2021 MediaTek Inc.
0004 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
0005
0006 #include <linux/clk-provider.h>
0007 #include <linux/platform_device.h>
0008
0009 #include "clk-mtk.h"
0010 #include "clk-gate.h"
0011
0012 #include <dt-bindings/clock/mt8192-clk.h>
0013
0014 static const struct mtk_gate_regs mm0_cg_regs = {
0015     .set_ofs = 0x104,
0016     .clr_ofs = 0x108,
0017     .sta_ofs = 0x100,
0018 };
0019
0020 static const struct mtk_gate_regs mm1_cg_regs = {
0021     .set_ofs = 0x114,
0022     .clr_ofs = 0x118,
0023     .sta_ofs = 0x110,
0024 };
0025
0026 static const struct mtk_gate_regs mm2_cg_regs = {
0027     .set_ofs = 0x1a4,
0028     .clr_ofs = 0x1a8,
0029     .sta_ofs = 0x1a0,
0030 };
0031
0032 #define GATE_MM0(_id, _name, _parent, _shift)   \
0033     GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
0034
0035 #define GATE_MM1(_id, _name, _parent, _shift)   \
0036     GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
0037
0038 #define GATE_MM2(_id, _name, _parent, _shift)   \
0039     GATE_MTK(_id, _name, _parent, &mm2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
0040
0041 static const struct mtk_gate mm_clks[] = {
0042     /* MM0 */
0043     GATE_MM0(CLK_MM_DISP_MUTEX0, "mm_disp_mutex0", "disp_sel", 0),
0044     GATE_MM0(CLK_MM_DISP_CONFIG, "mm_disp_config", "disp_sel", 1),
0045     GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "disp_sel", 2),
0046     GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "disp_sel", 3),
0047     GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "disp_sel", 4),
0048     GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "disp_sel", 5),
0049     GATE_MM0(CLK_MM_DISP_UFBC_WDMA0, "mm_disp_ufbc_wdma0", "disp_sel", 6),
0050     GATE_MM0(CLK_MM_DISP_RSZ0, "mm_disp_rsz0", "disp_sel", 7),
0051     GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "disp_sel", 8),
0052     GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "disp_sel", 9),
0053     GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "disp_sel", 10),
0054     GATE_MM0(CLK_MM_SMI_INFRA, "mm_smi_infra", "disp_sel", 11),
0055     GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "disp_sel", 12),
0056     GATE_MM0(CLK_MM_DISP_POSTMASK0, "mm_disp_postmask0", "disp_sel", 13),
0057     GATE_MM0(CLK_MM_DISP_DSC_WRAP0, "mm_disp_dsc_wrap0", "disp_sel", 14),
0058     GATE_MM0(CLK_MM_DSI0, "mm_dsi0", "disp_sel", 15),
0059     GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "disp_sel", 16),
0060     GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "disp_sel", 17),
0061     GATE_MM0(CLK_MM_DISP_FAKE_ENG0, "mm_disp_fake_eng0", "disp_sel", 18),
0062     GATE_MM0(CLK_MM_DISP_FAKE_ENG1, "mm_disp_fake_eng1", "disp_sel", 19),
0063     GATE_MM0(CLK_MM_MDP_TDSHP4, "mm_mdp_tdshp4", "disp_sel", 20),
0064     GATE_MM0(CLK_MM_MDP_RSZ4, "mm_mdp_rsz4", "disp_sel", 21),
0065     GATE_MM0(CLK_MM_MDP_AAL4, "mm_mdp_aal4", "disp_sel", 22),
0066     GATE_MM0(CLK_MM_MDP_HDR4, "mm_mdp_hdr4", "disp_sel", 23),
0067     GATE_MM0(CLK_MM_MDP_RDMA4, "mm_mdp_rdma4", "disp_sel", 24),
0068     GATE_MM0(CLK_MM_MDP_COLOR4, "mm_mdp_color4", "disp_sel", 25),
0069     GATE_MM0(CLK_MM_DISP_Y2R0, "mm_disp_y2r0", "disp_sel", 26),
0070     GATE_MM0(CLK_MM_SMI_GALS, "mm_smi_gals", "disp_sel", 27),
0071     GATE_MM0(CLK_MM_DISP_OVL2_2L, "mm_disp_ovl2_2l", "disp_sel", 28),
0072     GATE_MM0(CLK_MM_DISP_RDMA4, "mm_disp_rdma4", "disp_sel", 29),
0073     GATE_MM0(CLK_MM_DISP_DPI0, "mm_disp_dpi0", "disp_sel", 30),
0074     /* MM1 */
0075     GATE_MM1(CLK_MM_SMI_IOMMU, "mm_smi_iommu", "disp_sel", 0),
0076     /* MM2 */
0077     GATE_MM2(CLK_MM_DSI_DSI0, "mm_dsi_dsi0", "disp_sel", 0),
0078     GATE_MM2(CLK_MM_DPI_DPI0, "mm_dpi_dpi0", "dpi_sel", 8),
0079     GATE_MM2(CLK_MM_26MHZ, "mm_26mhz", "clk26m", 24),
0080     GATE_MM2(CLK_MM_32KHZ, "mm_32khz", "clk32k", 25),
0081 };
0082
0083 static int clk_mt8192_mm_probe(struct platform_device *pdev)
0084 {
0085     struct device *dev = &pdev->dev;
0086     struct device_node *node = dev->parent->of_node;
0087     struct clk_hw_onecell_data *clk_data;
0088     int r;
0089
0090     clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
0091     if (!clk_data)
0092         return -ENOMEM;
0093
0094     r = mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), clk_data);
0095     if (r)
0096         return r;
0097
0098     return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0099 }
0100
0101 static struct platform_driver clk_mt8192_mm_drv = {
0102     .probe = clk_mt8192_mm_probe,
0103     .driver = {
0104         .name = "clk-mt8192-mm",
0105     },
0106 };
0107
0108 builtin_platform_driver(clk_mt8192_mm_drv);