clk/mediatek/clk-mt8192-mdp.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // Copyright (c) 2021 MediaTek Inc.
0004 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
0005
0006 #include <linux/clk-provider.h>
0007 #include <linux/of_device.h>
0008 #include <linux/platform_device.h>
0009
0010 #include "clk-mtk.h"
0011 #include "clk-gate.h"
0012
0013 #include <dt-bindings/clock/mt8192-clk.h>
0014
0015 static const struct mtk_gate_regs mdp0_cg_regs = {
0016     .set_ofs = 0x104,
0017     .clr_ofs = 0x108,
0018     .sta_ofs = 0x100,
0019 };
0020
0021 static const struct mtk_gate_regs mdp1_cg_regs = {
0022     .set_ofs = 0x124,
0023     .clr_ofs = 0x128,
0024     .sta_ofs = 0x120,
0025 };
0026
0027 #define GATE_MDP0(_id, _name, _parent, _shift)  \
0028     GATE_MTK(_id, _name, _parent, &mdp0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
0029
0030 #define GATE_MDP1(_id, _name, _parent, _shift)  \
0031     GATE_MTK(_id, _name, _parent, &mdp1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
0032
0033 static const struct mtk_gate mdp_clks[] = {
0034     /* MDP0 */
0035     GATE_MDP0(CLK_MDP_RDMA0, "mdp_mdp_rdma0", "mdp_sel", 0),
0036     GATE_MDP0(CLK_MDP_TDSHP0, "mdp_mdp_tdshp0", "mdp_sel", 1),
0037     GATE_MDP0(CLK_MDP_IMG_DL_ASYNC0, "mdp_img_dl_async0", "mdp_sel", 2),
0038     GATE_MDP0(CLK_MDP_IMG_DL_ASYNC1, "mdp_img_dl_async1", "mdp_sel", 3),
0039     GATE_MDP0(CLK_MDP_RDMA1, "mdp_mdp_rdma1", "mdp_sel", 4),
0040     GATE_MDP0(CLK_MDP_TDSHP1, "mdp_mdp_tdshp1", "mdp_sel", 5),
0041     GATE_MDP0(CLK_MDP_SMI0, "mdp_smi0", "mdp_sel", 6),
0042     GATE_MDP0(CLK_MDP_APB_BUS, "mdp_apb_bus", "mdp_sel", 7),
0043     GATE_MDP0(CLK_MDP_WROT0, "mdp_mdp_wrot0", "mdp_sel", 8),
0044     GATE_MDP0(CLK_MDP_RSZ0, "mdp_mdp_rsz0", "mdp_sel", 9),
0045     GATE_MDP0(CLK_MDP_HDR0, "mdp_mdp_hdr0", "mdp_sel", 10),
0046     GATE_MDP0(CLK_MDP_MUTEX0, "mdp_mdp_mutex0", "mdp_sel", 11),
0047     GATE_MDP0(CLK_MDP_WROT1, "mdp_mdp_wrot1", "mdp_sel", 12),
0048     GATE_MDP0(CLK_MDP_RSZ1, "mdp_mdp_rsz1", "mdp_sel", 13),
0049     GATE_MDP0(CLK_MDP_HDR1, "mdp_mdp_hdr1", "mdp_sel", 14),
0050     GATE_MDP0(CLK_MDP_FAKE_ENG0, "mdp_mdp_fake_eng0", "mdp_sel", 15),
0051     GATE_MDP0(CLK_MDP_AAL0, "mdp_mdp_aal0", "mdp_sel", 16),
0052     GATE_MDP0(CLK_MDP_AAL1, "mdp_mdp_aal1", "mdp_sel", 17),
0053     GATE_MDP0(CLK_MDP_COLOR0, "mdp_mdp_color0", "mdp_sel", 18),
0054     GATE_MDP0(CLK_MDP_COLOR1, "mdp_mdp_color1", "mdp_sel", 19),
0055     /* MDP1 */
0056     GATE_MDP1(CLK_MDP_IMG_DL_RELAY0_ASYNC0, "mdp_img_dl_relay0_async0", "mdp_sel", 0),
0057     GATE_MDP1(CLK_MDP_IMG_DL_RELAY1_ASYNC1, "mdp_img_dl_relay1_async1", "mdp_sel", 8),
0058 };
0059
0060 static const struct mtk_clk_desc mdp_desc = {
0061     .clks = mdp_clks,
0062     .num_clks = ARRAY_SIZE(mdp_clks),
0063 };
0064
0065 static const struct of_device_id of_match_clk_mt8192_mdp[] = {
0066     {
0067         .compatible = "mediatek,mt8192-mdpsys",
0068         .data = &mdp_desc,
0069     }, {
0070         /* sentinel */
0071     }
0072 };
0073
0074 static struct platform_driver clk_mt8192_mdp_drv = {
0075     .probe = mtk_clk_simple_probe,
0076     .driver = {
0077         .name = "clk-mt8192-mdp",
0078         .of_match_table = of_match_clk_mt8192_mdp,
0079     },
0080 };
0081
0082 builtin_platform_driver(clk_mt8192_mdp_drv);