clk/mediatek/clk-mt8192-ipe.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // Copyright (c) 2021 MediaTek Inc.
0004 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
0005
0006 #include <linux/clk-provider.h>
0007 #include <linux/of_device.h>
0008 #include <linux/platform_device.h>
0009
0010 #include "clk-mtk.h"
0011 #include "clk-gate.h"
0012
0013 #include <dt-bindings/clock/mt8192-clk.h>
0014
0015 static const struct mtk_gate_regs ipe_cg_regs = {
0016     .set_ofs = 0x4,
0017     .clr_ofs = 0x8,
0018     .sta_ofs = 0x0,
0019 };
0020
0021 #define GATE_IPE(_id, _name, _parent, _shift)   \
0022     GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
0023
0024 static const struct mtk_gate ipe_clks[] = {
0025     GATE_IPE(CLK_IPE_LARB19, "ipe_larb19", "ipe_sel", 0),
0026     GATE_IPE(CLK_IPE_LARB20, "ipe_larb20", "ipe_sel", 1),
0027     GATE_IPE(CLK_IPE_SMI_SUBCOM, "ipe_smi_subcom", "ipe_sel", 2),
0028     GATE_IPE(CLK_IPE_FD, "ipe_fd", "ipe_sel", 3),
0029     GATE_IPE(CLK_IPE_FE, "ipe_fe", "ipe_sel", 4),
0030     GATE_IPE(CLK_IPE_RSC, "ipe_rsc", "ipe_sel", 5),
0031     GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "ipe_sel", 6),
0032     GATE_IPE(CLK_IPE_GALS, "ipe_gals", "ipe_sel", 8),
0033 };
0034
0035 static const struct mtk_clk_desc ipe_desc = {
0036     .clks = ipe_clks,
0037     .num_clks = ARRAY_SIZE(ipe_clks),
0038 };
0039
0040 static const struct of_device_id of_match_clk_mt8192_ipe[] = {
0041     {
0042         .compatible = "mediatek,mt8192-ipesys",
0043         .data = &ipe_desc,
0044     }, {
0045         /* sentinel */
0046     }
0047 };
0048
0049 static struct platform_driver clk_mt8192_ipe_drv = {
0050     .probe = mtk_clk_simple_probe,
0051     .driver = {
0052         .name = "clk-mt8192-ipe",
0053         .of_match_table = of_match_clk_mt8192_ipe,
0054     },
0055 };
0056
0057 builtin_platform_driver(clk_mt8192_ipe_drv);