clk/mediatek/clk-mt8192-imp_iic_wrap.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // Copyright (c) 2021 MediaTek Inc.
0004 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
0005
0006 #include <linux/clk-provider.h>
0007 #include <linux/of_device.h>
0008 #include <linux/platform_device.h>
0009
0010 #include "clk-mtk.h"
0011 #include "clk-gate.h"
0012
0013 #include <dt-bindings/clock/mt8192-clk.h>
0014
0015 static const struct mtk_gate_regs imp_iic_wrap_cg_regs = {
0016     .set_ofs = 0xe08,
0017     .clr_ofs = 0xe04,
0018     .sta_ofs = 0xe00,
0019 };
0020
0021 #define GATE_IMP_IIC_WRAP(_id, _name, _parent, _shift)          \
0022     GATE_MTK_FLAGS(_id, _name, _parent, &imp_iic_wrap_cg_regs, _shift,  \
0023         &mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE)
0024
0025 static const struct mtk_gate imp_iic_wrap_c_clks[] = {
0026     GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_I2C10, "imp_iic_wrap_c_i2c10", "infra_i2c0", 0),
0027     GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_I2C11, "imp_iic_wrap_c_i2c11", "infra_i2c0", 1),
0028     GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_I2C12, "imp_iic_wrap_c_i2c12", "infra_i2c0", 2),
0029     GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_I2C13, "imp_iic_wrap_c_i2c13", "infra_i2c0", 3),
0030 };
0031
0032 static const struct mtk_gate imp_iic_wrap_e_clks[] = {
0033     GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_E_I2C3, "imp_iic_wrap_e_i2c3", "infra_i2c0", 0),
0034 };
0035
0036 static const struct mtk_gate imp_iic_wrap_n_clks[] = {
0037     GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_N_I2C0, "imp_iic_wrap_n_i2c0", "infra_i2c0", 0),
0038     GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_N_I2C6, "imp_iic_wrap_n_i2c6", "infra_i2c0", 1),
0039 };
0040
0041 static const struct mtk_gate imp_iic_wrap_s_clks[] = {
0042     GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_I2C7, "imp_iic_wrap_s_i2c7", "infra_i2c0", 0),
0043     GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_I2C8, "imp_iic_wrap_s_i2c8", "infra_i2c0", 1),
0044     GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_I2C9, "imp_iic_wrap_s_i2c9", "infra_i2c0", 2),
0045 };
0046
0047 static const struct mtk_gate imp_iic_wrap_w_clks[] = {
0048     GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_I2C5, "imp_iic_wrap_w_i2c5", "infra_i2c0", 0),
0049 };
0050
0051 static const struct mtk_gate imp_iic_wrap_ws_clks[] = {
0052     GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_WS_I2C1, "imp_iic_wrap_ws_i2c1", "infra_i2c0", 0),
0053     GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_WS_I2C2, "imp_iic_wrap_ws_i2c2", "infra_i2c0", 1),
0054     GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_WS_I2C4, "imp_iic_wrap_ws_i2c4", "infra_i2c0", 2),
0055 };
0056
0057 static const struct mtk_clk_desc imp_iic_wrap_c_desc = {
0058     .clks = imp_iic_wrap_c_clks,
0059     .num_clks = ARRAY_SIZE(imp_iic_wrap_c_clks),
0060 };
0061
0062 static const struct mtk_clk_desc imp_iic_wrap_e_desc = {
0063     .clks = imp_iic_wrap_e_clks,
0064     .num_clks = ARRAY_SIZE(imp_iic_wrap_e_clks),
0065 };
0066
0067 static const struct mtk_clk_desc imp_iic_wrap_n_desc = {
0068     .clks = imp_iic_wrap_n_clks,
0069     .num_clks = ARRAY_SIZE(imp_iic_wrap_n_clks),
0070 };
0071
0072 static const struct mtk_clk_desc imp_iic_wrap_s_desc = {
0073     .clks = imp_iic_wrap_s_clks,
0074     .num_clks = ARRAY_SIZE(imp_iic_wrap_s_clks),
0075 };
0076
0077 static const struct mtk_clk_desc imp_iic_wrap_w_desc = {
0078     .clks = imp_iic_wrap_w_clks,
0079     .num_clks = ARRAY_SIZE(imp_iic_wrap_w_clks),
0080 };
0081
0082 static const struct mtk_clk_desc imp_iic_wrap_ws_desc = {
0083     .clks = imp_iic_wrap_ws_clks,
0084     .num_clks = ARRAY_SIZE(imp_iic_wrap_ws_clks),
0085 };
0086
0087 static const struct of_device_id of_match_clk_mt8192_imp_iic_wrap[] = {
0088     {
0089         .compatible = "mediatek,mt8192-imp_iic_wrap_c",
0090         .data = &imp_iic_wrap_c_desc,
0091     }, {
0092         .compatible = "mediatek,mt8192-imp_iic_wrap_e",
0093         .data = &imp_iic_wrap_e_desc,
0094     }, {
0095         .compatible = "mediatek,mt8192-imp_iic_wrap_n",
0096         .data = &imp_iic_wrap_n_desc,
0097     }, {
0098         .compatible = "mediatek,mt8192-imp_iic_wrap_s",
0099         .data = &imp_iic_wrap_s_desc,
0100     }, {
0101         .compatible = "mediatek,mt8192-imp_iic_wrap_w",
0102         .data = &imp_iic_wrap_w_desc,
0103     }, {
0104         .compatible = "mediatek,mt8192-imp_iic_wrap_ws",
0105         .data = &imp_iic_wrap_ws_desc,
0106     }, {
0107         /* sentinel */
0108     }
0109 };
0110
0111 static struct platform_driver clk_mt8192_imp_iic_wrap_drv = {
0112     .probe = mtk_clk_simple_probe,
0113     .driver = {
0114         .name = "clk-mt8192-imp_iic_wrap",
0115         .of_match_table = of_match_clk_mt8192_imp_iic_wrap,
0116     },
0117 };
0118
0119 builtin_platform_driver(clk_mt8192_imp_iic_wrap_drv);