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0006 #include <linux/clk-provider.h>
0007 #include <linux/of_device.h>
0008 #include <linux/platform_device.h>
0009
0010 #include "clk-mtk.h"
0011 #include "clk-gate.h"
0012
0013 #include <dt-bindings/clock/mt8192-clk.h>
0014
0015 static const struct mtk_gate_regs img_cg_regs = {
0016 .set_ofs = 0x4,
0017 .clr_ofs = 0x8,
0018 .sta_ofs = 0x0,
0019 };
0020
0021 #define GATE_IMG(_id, _name, _parent, _shift) \
0022 GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
0023
0024 static const struct mtk_gate img_clks[] = {
0025 GATE_IMG(CLK_IMG_LARB9, "img_larb9", "img1_sel", 0),
0026 GATE_IMG(CLK_IMG_LARB10, "img_larb10", "img1_sel", 1),
0027 GATE_IMG(CLK_IMG_DIP, "img_dip", "img1_sel", 2),
0028 GATE_IMG(CLK_IMG_GALS, "img_gals", "img1_sel", 12),
0029 };
0030
0031 static const struct mtk_gate img2_clks[] = {
0032 GATE_IMG(CLK_IMG2_LARB11, "img2_larb11", "img1_sel", 0),
0033 GATE_IMG(CLK_IMG2_LARB12, "img2_larb12", "img1_sel", 1),
0034 GATE_IMG(CLK_IMG2_MFB, "img2_mfb", "img1_sel", 6),
0035 GATE_IMG(CLK_IMG2_WPE, "img2_wpe", "img1_sel", 7),
0036 GATE_IMG(CLK_IMG2_MSS, "img2_mss", "img1_sel", 8),
0037 GATE_IMG(CLK_IMG2_GALS, "img2_gals", "img1_sel", 12),
0038 };
0039
0040 static const struct mtk_clk_desc img_desc = {
0041 .clks = img_clks,
0042 .num_clks = ARRAY_SIZE(img_clks),
0043 };
0044
0045 static const struct mtk_clk_desc img2_desc = {
0046 .clks = img2_clks,
0047 .num_clks = ARRAY_SIZE(img2_clks),
0048 };
0049
0050 static const struct of_device_id of_match_clk_mt8192_img[] = {
0051 {
0052 .compatible = "mediatek,mt8192-imgsys",
0053 .data = &img_desc,
0054 }, {
0055 .compatible = "mediatek,mt8192-imgsys2",
0056 .data = &img2_desc,
0057 }, {
0058
0059 }
0060 };
0061
0062 static struct platform_driver clk_mt8192_img_drv = {
0063 .probe = mtk_clk_simple_probe,
0064 .driver = {
0065 .name = "clk-mt8192-img",
0066 .of_match_table = of_match_clk_mt8192_img,
0067 },
0068 };
0069
0070 builtin_platform_driver(clk_mt8192_img_drv);