clk/mediatek/clk-mt8192-cam.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // Copyright (c) 2021 MediaTek Inc.
0004 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
0005
0006 #include <linux/clk-provider.h>
0007 #include <linux/of_device.h>
0008 #include <linux/platform_device.h>
0009
0010 #include "clk-mtk.h"
0011 #include "clk-gate.h"
0012
0013 #include <dt-bindings/clock/mt8192-clk.h>
0014
0015 static const struct mtk_gate_regs cam_cg_regs = {
0016     .set_ofs = 0x4,
0017     .clr_ofs = 0x8,
0018     .sta_ofs = 0x0,
0019 };
0020
0021 #define GATE_CAM(_id, _name, _parent, _shift)   \
0022     GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
0023
0024 static const struct mtk_gate cam_clks[] = {
0025     GATE_CAM(CLK_CAM_LARB13, "cam_larb13", "cam_sel", 0),
0026     GATE_CAM(CLK_CAM_DFP_VAD, "cam_dfp_vad", "cam_sel", 1),
0027     GATE_CAM(CLK_CAM_LARB14, "cam_larb14", "cam_sel", 2),
0028     GATE_CAM(CLK_CAM_CAM, "cam_cam", "cam_sel", 6),
0029     GATE_CAM(CLK_CAM_CAMTG, "cam_camtg", "cam_sel", 7),
0030     GATE_CAM(CLK_CAM_SENINF, "cam_seninf", "cam_sel", 8),
0031     GATE_CAM(CLK_CAM_CAMSV0, "cam_camsv0", "cam_sel", 9),
0032     GATE_CAM(CLK_CAM_CAMSV1, "cam_camsv1", "cam_sel", 10),
0033     GATE_CAM(CLK_CAM_CAMSV2, "cam_camsv2", "cam_sel", 11),
0034     GATE_CAM(CLK_CAM_CAMSV3, "cam_camsv3", "cam_sel", 12),
0035     GATE_CAM(CLK_CAM_CCU0, "cam_ccu0", "cam_sel", 13),
0036     GATE_CAM(CLK_CAM_CCU1, "cam_ccu1", "cam_sel", 14),
0037     GATE_CAM(CLK_CAM_MRAW0, "cam_mraw0", "cam_sel", 15),
0038     GATE_CAM(CLK_CAM_FAKE_ENG, "cam_fake_eng", "cam_sel", 17),
0039     GATE_CAM(CLK_CAM_CCU_GALS, "cam_ccu_gals", "cam_sel", 18),
0040     GATE_CAM(CLK_CAM_CAM2MM_GALS, "cam2mm_gals", "cam_sel", 19),
0041 };
0042
0043 static const struct mtk_gate cam_rawa_clks[] = {
0044     GATE_CAM(CLK_CAM_RAWA_LARBX, "cam_rawa_larbx", "cam_sel", 0),
0045     GATE_CAM(CLK_CAM_RAWA_CAM, "cam_rawa_cam", "cam_sel", 1),
0046     GATE_CAM(CLK_CAM_RAWA_CAMTG, "cam_rawa_camtg", "cam_sel", 2),
0047 };
0048
0049 static const struct mtk_gate cam_rawb_clks[] = {
0050     GATE_CAM(CLK_CAM_RAWB_LARBX, "cam_rawb_larbx", "cam_sel", 0),
0051     GATE_CAM(CLK_CAM_RAWB_CAM, "cam_rawb_cam", "cam_sel", 1),
0052     GATE_CAM(CLK_CAM_RAWB_CAMTG, "cam_rawb_camtg", "cam_sel", 2),
0053 };
0054
0055 static const struct mtk_gate cam_rawc_clks[] = {
0056     GATE_CAM(CLK_CAM_RAWC_LARBX, "cam_rawc_larbx", "cam_sel", 0),
0057     GATE_CAM(CLK_CAM_RAWC_CAM, "cam_rawc_cam", "cam_sel", 1),
0058     GATE_CAM(CLK_CAM_RAWC_CAMTG, "cam_rawc_camtg", "cam_sel", 2),
0059 };
0060
0061 static const struct mtk_clk_desc cam_desc = {
0062     .clks = cam_clks,
0063     .num_clks = ARRAY_SIZE(cam_clks),
0064 };
0065
0066 static const struct mtk_clk_desc cam_rawa_desc = {
0067     .clks = cam_rawa_clks,
0068     .num_clks = ARRAY_SIZE(cam_rawa_clks),
0069 };
0070
0071 static const struct mtk_clk_desc cam_rawb_desc = {
0072     .clks = cam_rawb_clks,
0073     .num_clks = ARRAY_SIZE(cam_rawb_clks),
0074 };
0075
0076 static const struct mtk_clk_desc cam_rawc_desc = {
0077     .clks = cam_rawc_clks,
0078     .num_clks = ARRAY_SIZE(cam_rawc_clks),
0079 };
0080
0081 static const struct of_device_id of_match_clk_mt8192_cam[] = {
0082     {
0083         .compatible = "mediatek,mt8192-camsys",
0084         .data = &cam_desc,
0085     }, {
0086         .compatible = "mediatek,mt8192-camsys_rawa",
0087         .data = &cam_rawa_desc,
0088     }, {
0089         .compatible = "mediatek,mt8192-camsys_rawb",
0090         .data = &cam_rawb_desc,
0091     }, {
0092         .compatible = "mediatek,mt8192-camsys_rawc",
0093         .data = &cam_rawc_desc,
0094     }, {
0095         /* sentinel */
0096     }
0097 };
0098
0099 static struct platform_driver clk_mt8192_cam_drv = {
0100     .probe = mtk_clk_simple_probe,
0101     .driver = {
0102         .name = "clk-mt8192-cam",
0103         .of_match_table = of_match_clk_mt8192_cam,
0104     },
0105 };
0106
0107 builtin_platform_driver(clk_mt8192_cam_drv);