clk/mediatek/clk-mt8192-aud.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // Copyright (c) 2021 MediaTek Inc.
0004 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
0005
0006 #include <linux/clk-provider.h>
0007 #include <linux/of_platform.h>
0008 #include <linux/platform_device.h>
0009
0010 #include "clk-mtk.h"
0011 #include "clk-gate.h"
0012
0013 #include <dt-bindings/clock/mt8192-clk.h>
0014
0015 static const struct mtk_gate_regs aud0_cg_regs = {
0016     .set_ofs = 0x0,
0017     .clr_ofs = 0x0,
0018     .sta_ofs = 0x0,
0019 };
0020
0021 static const struct mtk_gate_regs aud1_cg_regs = {
0022     .set_ofs = 0x4,
0023     .clr_ofs = 0x4,
0024     .sta_ofs = 0x4,
0025 };
0026
0027 static const struct mtk_gate_regs aud2_cg_regs = {
0028     .set_ofs = 0x8,
0029     .clr_ofs = 0x8,
0030     .sta_ofs = 0x8,
0031 };
0032
0033 #define GATE_AUD0(_id, _name, _parent, _shift)  \
0034     GATE_MTK(_id, _name, _parent, &aud0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
0035
0036 #define GATE_AUD1(_id, _name, _parent, _shift)  \
0037     GATE_MTK(_id, _name, _parent, &aud1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
0038
0039 #define GATE_AUD2(_id, _name, _parent, _shift)  \
0040     GATE_MTK(_id, _name, _parent, &aud2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
0041
0042 static const struct mtk_gate aud_clks[] = {
0043     /* AUD0 */
0044     GATE_AUD0(CLK_AUD_AFE, "aud_afe", "audio_sel", 2),
0045     GATE_AUD0(CLK_AUD_22M, "aud_22m", "aud_engen1_sel", 8),
0046     GATE_AUD0(CLK_AUD_24M, "aud_24m", "aud_engen2_sel", 9),
0047     GATE_AUD0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "aud_engen2_sel", 18),
0048     GATE_AUD0(CLK_AUD_APLL_TUNER, "aud_apll_tuner", "aud_engen1_sel", 19),
0049     GATE_AUD0(CLK_AUD_TDM, "aud_tdm", "aud_1_sel", 20),
0050     GATE_AUD0(CLK_AUD_ADC, "aud_adc", "audio_sel", 24),
0051     GATE_AUD0(CLK_AUD_DAC, "aud_dac", "audio_sel", 25),
0052     GATE_AUD0(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "audio_sel", 26),
0053     GATE_AUD0(CLK_AUD_TML, "aud_tml", "audio_sel", 27),
0054     GATE_AUD0(CLK_AUD_NLE, "aud_nle", "audio_sel", 28),
0055     /* AUD1 */
0056     GATE_AUD1(CLK_AUD_I2S1_B, "aud_i2s1_b", "audio_sel", 4),
0057     GATE_AUD1(CLK_AUD_I2S2_B, "aud_i2s2_b", "audio_sel", 5),
0058     GATE_AUD1(CLK_AUD_I2S3_B, "aud_i2s3_b", "audio_sel", 6),
0059     GATE_AUD1(CLK_AUD_I2S4_B, "aud_i2s4_b", "audio_sel", 7),
0060     GATE_AUD1(CLK_AUD_CONNSYS_I2S_ASRC, "aud_connsys_i2s_asrc", "audio_sel", 12),
0061     GATE_AUD1(CLK_AUD_GENERAL1_ASRC, "aud_general1_asrc", "audio_sel", 13),
0062     GATE_AUD1(CLK_AUD_GENERAL2_ASRC, "aud_general2_asrc", "audio_sel", 14),
0063     GATE_AUD1(CLK_AUD_DAC_HIRES, "aud_dac_hires", "audio_h_sel", 15),
0064     GATE_AUD1(CLK_AUD_ADC_HIRES, "aud_adc_hires", "audio_h_sel", 16),
0065     GATE_AUD1(CLK_AUD_ADC_HIRES_TML, "aud_adc_hires_tml", "audio_h_sel", 17),
0066     GATE_AUD1(CLK_AUD_ADDA6_ADC, "aud_adda6_adc", "audio_sel", 20),
0067     GATE_AUD1(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires", "audio_h_sel", 21),
0068     GATE_AUD1(CLK_AUD_3RD_DAC, "aud_3rd_dac", "audio_sel", 28),
0069     GATE_AUD1(CLK_AUD_3RD_DAC_PREDIS, "aud_3rd_dac_predis", "audio_sel", 29),
0070     GATE_AUD1(CLK_AUD_3RD_DAC_TML, "aud_3rd_dac_tml", "audio_sel", 30),
0071     GATE_AUD1(CLK_AUD_3RD_DAC_HIRES, "aud_3rd_dac_hires", "audio_h_sel", 31),
0072     /* AUD2 */
0073     GATE_AUD2(CLK_AUD_I2S5_B, "aud_i2s5_b", "audio_sel", 0),
0074     GATE_AUD2(CLK_AUD_I2S6_B, "aud_i2s6_b", "audio_sel", 1),
0075     GATE_AUD2(CLK_AUD_I2S7_B, "aud_i2s7_b", "audio_sel", 2),
0076     GATE_AUD2(CLK_AUD_I2S8_B, "aud_i2s8_b", "audio_sel", 3),
0077     GATE_AUD2(CLK_AUD_I2S9_B, "aud_i2s9_b", "audio_sel", 4),
0078 };
0079
0080 static int clk_mt8192_aud_probe(struct platform_device *pdev)
0081 {
0082     struct clk_hw_onecell_data *clk_data;
0083     struct device_node *node = pdev->dev.of_node;
0084     int r;
0085
0086     clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);
0087     if (!clk_data)
0088         return -ENOMEM;
0089
0090     r = mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), clk_data);
0091     if (r)
0092         return r;
0093
0094     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0095     if (r)
0096         return r;
0097
0098     r = devm_of_platform_populate(&pdev->dev);
0099     if (r)
0100         of_clk_del_provider(node);
0101
0102     return r;
0103 }
0104
0105 static const struct of_device_id of_match_clk_mt8192_aud[] = {
0106     { .compatible = "mediatek,mt8192-audsys", },
0107     {}
0108 };
0109
0110 static struct platform_driver clk_mt8192_aud_drv = {
0111     .probe = clk_mt8192_aud_probe,
0112     .driver = {
0113         .name = "clk-mt8192-aud",
0114         .of_match_table = of_match_clk_mt8192_aud,
0115     },
0116 };
0117
0118 builtin_platform_driver(clk_mt8192_aud_drv);