clk/mediatek/clk-mt8186-wpe.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // Copyright (c) 2022 MediaTek Inc.
0004 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
0005
0006 #include <linux/clk-provider.h>
0007 #include <linux/platform_device.h>
0008 #include <dt-bindings/clock/mt8186-clk.h>
0009
0010 #include "clk-gate.h"
0011 #include "clk-mtk.h"
0012
0013 static const struct mtk_gate_regs wpe_cg_regs = {
0014     .set_ofs = 0x0,
0015     .clr_ofs = 0x0,
0016     .sta_ofs = 0x0,
0017 };
0018
0019 #define GATE_WPE(_id, _name, _parent, _shift)           \
0020     GATE_MTK(_id, _name, _parent, &wpe_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
0021
0022 static const struct mtk_gate wpe_clks[] = {
0023     GATE_WPE(CLK_WPE_CK_EN, "wpe", "top_wpe", 17),
0024     GATE_WPE(CLK_WPE_SMI_LARB8_CK_EN, "wpe_smi_larb8", "top_wpe", 19),
0025     GATE_WPE(CLK_WPE_SYS_EVENT_TX_CK_EN, "wpe_sys_event_tx", "top_wpe", 20),
0026     GATE_WPE(CLK_WPE_SMI_LARB8_PCLK_EN, "wpe_smi_larb8_p_en", "top_wpe", 25),
0027 };
0028
0029 static const struct mtk_clk_desc wpe_desc = {
0030     .clks = wpe_clks,
0031     .num_clks = ARRAY_SIZE(wpe_clks),
0032 };
0033
0034 static const struct of_device_id of_match_clk_mt8186_wpe[] = {
0035     {
0036         .compatible = "mediatek,mt8186-wpesys",
0037         .data = &wpe_desc,
0038     }, {
0039         /* sentinel */
0040     }
0041 };
0042
0043 static struct platform_driver clk_mt8186_wpe_drv = {
0044     .probe = mtk_clk_simple_probe,
0045     .remove = mtk_clk_simple_remove,
0046     .driver = {
0047         .name = "clk-mt8186-wpe",
0048         .of_match_table = of_match_clk_mt8186_wpe,
0049     },
0050 };
0051 builtin_platform_driver(clk_mt8186_wpe_drv);