clk/mediatek/clk-mt8186-vdec.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // Copyright (c) 2022 MediaTek Inc.
0004 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
0005
0006 #include <linux/clk-provider.h>
0007 #include <linux/module.h>
0008 #include <linux/platform_device.h>
0009
0010 #include "clk-mtk.h"
0011 #include "clk-gate.h"
0012
0013 #include <dt-bindings/clock/mt8186-clk.h>
0014
0015 static const struct mtk_gate_regs vdec0_cg_regs = {
0016     .set_ofs = 0x0,
0017     .clr_ofs = 0x4,
0018     .sta_ofs = 0x0,
0019 };
0020
0021 static const struct mtk_gate_regs vdec1_cg_regs = {
0022     .set_ofs = 0x190,
0023     .clr_ofs = 0x190,
0024     .sta_ofs = 0x190,
0025 };
0026
0027 static const struct mtk_gate_regs vdec2_cg_regs = {
0028     .set_ofs = 0x200,
0029     .clr_ofs = 0x204,
0030     .sta_ofs = 0x200,
0031 };
0032
0033 static const struct mtk_gate_regs vdec3_cg_regs = {
0034     .set_ofs = 0x8,
0035     .clr_ofs = 0xc,
0036     .sta_ofs = 0x8,
0037 };
0038
0039 #define GATE_VDEC0(_id, _name, _parent, _shift)         \
0040     GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
0041
0042 #define GATE_VDEC1(_id, _name, _parent, _shift)         \
0043     GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
0044
0045 #define GATE_VDEC2(_id, _name, _parent, _shift)         \
0046     GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
0047
0048 #define GATE_VDEC3(_id, _name, _parent, _shift)         \
0049     GATE_MTK(_id, _name, _parent, &vdec3_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
0050
0051 static const struct mtk_gate vdec_clks[] = {
0052     /* VDEC0 */
0053     GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "top_vdec", 0),
0054     GATE_VDEC0(CLK_VDEC_ACTIVE, "vdec_active", "top_vdec", 4),
0055     GATE_VDEC0(CLK_VDEC_CKEN_ENG, "vdec_cken_eng", "top_vdec", 8),
0056     /* VDEC1 */
0057     GATE_VDEC1(CLK_VDEC_MINI_MDP_CKEN_CFG_RG, "vdec_mini_mdp_cken_cfg_rg", "top_vdec", 0),
0058     /* VDEC2 */
0059     GATE_VDEC2(CLK_VDEC_LAT_CKEN, "vdec_lat_cken", "top_vdec", 0),
0060     GATE_VDEC2(CLK_VDEC_LAT_ACTIVE, "vdec_lat_active", "top_vdec", 4),
0061     GATE_VDEC2(CLK_VDEC_LAT_CKEN_ENG, "vdec_lat_cken_eng", "top_vdec", 8),
0062     /* VDEC3 */
0063     GATE_VDEC3(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "top_vdec", 0),
0064 };
0065
0066 static const struct mtk_clk_desc vdec_desc = {
0067     .clks = vdec_clks,
0068     .num_clks = ARRAY_SIZE(vdec_clks),
0069 };
0070
0071 static const struct of_device_id of_match_clk_mt8186_vdec[] = {
0072     {
0073         .compatible = "mediatek,mt8186-vdecsys",
0074         .data = &vdec_desc,
0075     }, {
0076         /* sentinel */
0077     }
0078 };
0079
0080 static struct platform_driver clk_mt8186_vdec_drv = {
0081     .probe = mtk_clk_simple_probe,
0082     .remove = mtk_clk_simple_remove,
0083     .driver = {
0084         .name = "clk-mt8186-vdec",
0085         .of_match_table = of_match_clk_mt8186_vdec,
0086     },
0087 };
0088 builtin_platform_driver(clk_mt8186_vdec_drv);