clk/mediatek/clk-mt8186-topckgen.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // Copyright (c) 2022 MediaTek Inc.
0004 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
0005
0006 #include <linux/clk-provider.h>
0007 #include <linux/platform_device.h>
0008 #include <dt-bindings/clock/mt8186-clk.h>
0009
0010 #include "clk-mtk.h"
0011 #include "clk-mux.h"
0012
0013 static DEFINE_SPINLOCK(mt8186_clk_lock);
0014
0015 static const struct mtk_fixed_clk top_fixed_clks[] = {
0016     FIXED_CLK(CLK_TOP_ULPOSC1, "ulposc1", NULL, 250000000),
0017     FIXED_CLK(CLK_TOP_466M_FMEM, "hd_466m_fmem_ck", NULL, 466000000),
0018     FIXED_CLK(CLK_TOP_MPLL, "mpll", NULL, 208000000),
0019 };
0020
0021 static const struct mtk_fixed_factor top_divs[] = {
0022     FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2),
0023     FACTOR(CLK_TOP_MAINPLL_D2_D2, "mainpll_d2_d2", "mainpll_d2", 1, 2),
0024     FACTOR(CLK_TOP_MAINPLL_D2_D4, "mainpll_d2_d4", "mainpll_d2", 1, 4),
0025     FACTOR(CLK_TOP_MAINPLL_D2_D16, "mainpll_d2_d16", "mainpll_d2", 1, 16),
0026     FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
0027     FACTOR(CLK_TOP_MAINPLL_D3_D2, "mainpll_d3_d2", "mainpll_d3", 1, 2),
0028     FACTOR(CLK_TOP_MAINPLL_D3_D4, "mainpll_d3_d4", "mainpll_d3", 1, 4),
0029     FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
0030     FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2),
0031     FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4),
0032     FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
0033     FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2),
0034     FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4),
0035     FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2),
0036     FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
0037     FACTOR(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 2),
0038     FACTOR(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 4),
0039     FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
0040     FACTOR(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 2),
0041     FACTOR(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 4),
0042     FACTOR(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 8),
0043     FACTOR(CLK_TOP_UNIVPLL_D3_D32, "univpll_d3_d32", "univpll_d3", 1, 32),
0044     FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
0045     FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2),
0046     FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
0047     FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
0048     FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univ2pll", 1, 13),
0049     FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4),
0050     FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8),
0051     FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16),
0052     FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32),
0053     FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2),
0054     FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
0055     FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8),
0056     FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
0057     FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
0058     FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8),
0059     FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
0060     FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2),
0061     FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
0062     FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8),
0063     FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16),
0064     FACTOR(CLK_TOP_TVDPLL_D32, "tvdpll_d32", "tvdpll", 1, 32),
0065     FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
0066     FACTOR(CLK_TOP_ULPOSC1_D2, "ulposc1_d2", "ulposc1", 1, 2),
0067     FACTOR(CLK_TOP_ULPOSC1_D4, "ulposc1_d4", "ulposc1", 1, 4),
0068     FACTOR(CLK_TOP_ULPOSC1_D8, "ulposc1_d8", "ulposc1", 1, 8),
0069     FACTOR(CLK_TOP_ULPOSC1_D10, "ulposc1_d10", "ulposc1", 1, 10),
0070     FACTOR(CLK_TOP_ULPOSC1_D16, "ulposc1_d16", "ulposc1", 1, 16),
0071     FACTOR(CLK_TOP_ULPOSC1_D32, "ulposc1_d32", "ulposc1", 1, 32),
0072     FACTOR(CLK_TOP_ADSPPLL_D2, "adsppll_d2", "adsppll", 1, 2),
0073     FACTOR(CLK_TOP_ADSPPLL_D4, "adsppll_d4", "adsppll", 1, 4),
0074     FACTOR(CLK_TOP_ADSPPLL_D8, "adsppll_d8", "adsppll", 1, 8),
0075     FACTOR(CLK_TOP_NNAPLL_D2, "nnapll_d2", "nnapll", 1, 2),
0076     FACTOR(CLK_TOP_NNAPLL_D4, "nnapll_d4", "nnapll", 1, 4),
0077     FACTOR(CLK_TOP_NNAPLL_D8, "nnapll_d8", "nnapll", 1, 8),
0078     FACTOR(CLK_TOP_NNA2PLL_D2, "nna2pll_d2", "nna2pll", 1, 2),
0079     FACTOR(CLK_TOP_NNA2PLL_D4, "nna2pll_d4", "nna2pll", 1, 4),
0080     FACTOR(CLK_TOP_NNA2PLL_D8, "nna2pll_d8", "nna2pll", 1, 8),
0081     FACTOR(CLK_TOP_F_BIST2FPC, "f_bist2fpc_ck", "univpll_d3_d2", 1, 1),
0082 };
0083
0084 static const char * const axi_parents[] = {
0085     "clk26m",
0086     "mainpll_d7",
0087     "mainpll_d2_d4",
0088     "univpll_d7"
0089 };
0090
0091 static const char * const scp_parents[] = {
0092     "clk26m",
0093     "mainpll_d2_d4",
0094     "mainpll_d5",
0095     "mainpll_d2_d2",
0096     "mainpll_d3",
0097     "univpll_d3"
0098 };
0099
0100 static const char * const mfg_parents[] = {
0101     "clk26m",
0102     "mfgpll",
0103     "mainpll_d3",
0104     "mainpll_d5"
0105 };
0106
0107 static const char * const camtg_parents[] = {
0108     "clk26m",
0109     "univpll_192m_d8",
0110     "univpll_d3_d8",
0111     "univpll_192m_d4",
0112     "univpll_d3_d32",
0113     "univpll_192m_d16",
0114     "univpll_192m_d32"
0115 };
0116
0117 static const char * const uart_parents[] = {
0118     "clk26m",
0119     "univpll_d3_d8"
0120 };
0121
0122 static const char * const spi_parents[] = {
0123     "clk26m",
0124     "mainpll_d5_d4",
0125     "mainpll_d3_d4",
0126     "mainpll_d5_d2",
0127     "mainpll_d2_d4",
0128     "mainpll_d7",
0129     "mainpll_d3_d2",
0130     "mainpll_d5"
0131 };
0132
0133 static const char * const msdc5hclk_parents[] = {
0134     "clk26m",
0135     "mainpll_d2_d2",
0136     "mainpll_d7",
0137     "mainpll_d3_d2"
0138 };
0139
0140 static const char * const msdc50_0_parents[] = {
0141     "clk26m",
0142     "msdcpll",
0143     "univpll_d3",
0144     "msdcpll_d2",
0145     "mainpll_d7",
0146     "mainpll_d3_d2",
0147     "univpll_d2_d2"
0148 };
0149
0150 static const char * const msdc30_1_parents[] = {
0151     "clk26m",
0152     "msdcpll_d2",
0153     "univpll_d3_d2",
0154     "mainpll_d3_d2",
0155     "mainpll_d7"
0156 };
0157
0158 static const char * const audio_parents[] = {
0159     "clk26m",
0160     "mainpll_d5_d4",
0161     "mainpll_d7_d4",
0162     "mainpll_d2_d16"
0163 };
0164
0165 static const char * const aud_intbus_parents[] = {
0166     "clk26m",
0167     "mainpll_d2_d4",
0168     "mainpll_d7_d2"
0169 };
0170
0171 static const char * const aud_1_parents[] = {
0172     "clk26m",
0173     "apll1"
0174 };
0175
0176 static const char * const aud_2_parents[] = {
0177     "clk26m",
0178     "apll2"
0179 };
0180
0181 static const char * const aud_engen1_parents[] = {
0182     "clk26m",
0183     "apll1_d2",
0184     "apll1_d4",
0185     "apll1_d8"
0186 };
0187
0188 static const char * const aud_engen2_parents[] = {
0189     "clk26m",
0190     "apll2_d2",
0191     "apll2_d4",
0192     "apll2_d8"
0193 };
0194
0195 static const char * const disp_pwm_parents[] = {
0196     "clk26m",
0197     "univpll_d5_d2",
0198     "univpll_d3_d4",
0199     "ulposc1_d2",
0200     "ulposc1_d8"
0201 };
0202
0203 static const char * const sspm_parents[] = {
0204     "clk26m",
0205     "mainpll_d2_d2",
0206     "mainpll_d3_d2",
0207     "mainpll_d5",
0208     "mainpll_d3"
0209 };
0210
0211 static const char * const dxcc_parents[] = {
0212     "clk26m",
0213     "mainpll_d2_d2",
0214     "mainpll_d2_d4"
0215 };
0216
0217 static const char * const usb_parents[] = {
0218     "clk26m",
0219     "univpll_d5_d4",
0220     "univpll_d5_d2"
0221 };
0222
0223 static const char * const srck_parents[] = {
0224     "clk32k",
0225     "clk26m",
0226     "ulposc1_d10"
0227 };
0228
0229 static const char * const spm_parents[] = {
0230     "clk32k",
0231     "ulposc1_d10",
0232     "clk26m",
0233     "mainpll_d7_d2"
0234 };
0235
0236 static const char * const i2c_parents[] = {
0237     "clk26m",
0238     "univpll_d5_d4",
0239     "univpll_d3_d4",
0240     "univpll_d5_d2"
0241 };
0242
0243 static const char * const pwm_parents[] = {
0244     "clk26m",
0245     "univpll_d3_d8",
0246     "univpll_d3_d4",
0247     "univpll_d2_d4"
0248 };
0249
0250 static const char * const seninf_parents[] = {
0251     "clk26m",
0252     "univpll_d2_d4",
0253     "univpll_d2_d2",
0254     "univpll_d3_d2"
0255 };
0256
0257 static const char * const aes_msdcfde_parents[] = {
0258     "clk26m",
0259     "univpll_d3",
0260     "mainpll_d3",
0261     "univpll_d2_d2",
0262     "mainpll_d2_d2",
0263     "mainpll_d2_d4"
0264 };
0265
0266 static const char * const pwrap_ulposc_parents[] = {
0267     "clk26m",
0268     "univpll_d5_d4",
0269     "ulposc1_d4",
0270     "ulposc1_d8",
0271     "ulposc1_d10",
0272     "ulposc1_d16",
0273     "ulposc1_d32"
0274 };
0275
0276 static const char * const camtm_parents[] = {
0277     "clk26m",
0278     "univpll_d2_d4",
0279     "univpll_d3_d2"
0280 };
0281
0282 static const char * const venc_parents[] = {
0283     "clk26m",
0284     "mmpll",
0285     "mainpll_d2_d2",
0286     "mainpll_d2",
0287     "univpll_d3",
0288     "univpll_d2_d2",
0289     "mainpll_d3",
0290     "mmpll"
0291 };
0292
0293 static const char * const isp_parents[] = {
0294     "clk26m",
0295     "mainpll_d2",
0296     "mainpll_d2_d2",
0297     "univpll_d3",
0298     "mainpll_d3",
0299     "mmpll",
0300     "univpll_d5",
0301     "univpll_d2_d2",
0302     "mmpll_d2"
0303 };
0304
0305 static const char * const dpmaif_parents[] = {
0306     "clk26m",
0307     "univpll_d2_d2",
0308     "mainpll_d3",
0309     "mainpll_d2_d2",
0310     "univpll_d3_d2"
0311 };
0312
0313 static const char * const vdec_parents[] = {
0314     "clk26m",
0315     "mainpll_d3",
0316     "mainpll_d2_d2",
0317     "univpll_d5",
0318     "mainpll_d2",
0319     "univpll_d3",
0320     "univpll_d2_d2"
0321 };
0322
0323 static const char * const disp_parents[] = {
0324     "clk26m",
0325     "univpll_d3_d2",
0326     "mainpll_d5",
0327     "univpll_d5",
0328     "univpll_d2_d2",
0329     "mainpll_d3",
0330     "univpll_d3",
0331     "mainpll_d2",
0332     "mmpll"
0333 };
0334
0335 static const char * const mdp_parents[] = {
0336     "clk26m",
0337     "mainpll_d5",
0338     "univpll_d5",
0339     "mainpll_d2_d2",
0340     "univpll_d2_d2",
0341     "mainpll_d3",
0342     "univpll_d3",
0343     "mainpll_d2",
0344     "mmpll"
0345 };
0346
0347 static const char * const audio_h_parents[] = {
0348     "clk26m",
0349     "univpll_d7",
0350     "apll1",
0351     "apll2"
0352 };
0353
0354 static const char * const ufs_parents[] = {
0355     "clk26m",
0356     "mainpll_d7",
0357     "univpll_d2_d4",
0358     "mainpll_d2_d4"
0359 };
0360
0361 static const char * const aes_fde_parents[] = {
0362     "clk26m",
0363     "univpll_d3",
0364     "mainpll_d2_d2",
0365     "univpll_d5"
0366 };
0367
0368 static const char * const audiodsp_parents[] = {
0369     "clk26m",
0370     "ulposc1_d10",
0371     "adsppll",
0372     "adsppll_d2",
0373     "adsppll_d4",
0374     "adsppll_d8"
0375 };
0376
0377 static const char * const dvfsrc_parents[] = {
0378     "clk26m",
0379     "ulposc1_d10",
0380 };
0381
0382 static const char * const dsi_occ_parents[] = {
0383     "clk26m",
0384     "univpll_d3_d2",
0385     "mpll",
0386     "mainpll_d5"
0387 };
0388
0389 static const char * const spmi_mst_parents[] = {
0390     "clk26m",
0391     "univpll_d5_d4",
0392     "ulposc1_d4",
0393     "ulposc1_d8",
0394     "ulposc1_d10",
0395     "ulposc1_d16",
0396     "ulposc1_d32"
0397 };
0398
0399 static const char * const spinor_parents[] = {
0400     "clk26m",
0401     "clk13m",
0402     "mainpll_d7_d4",
0403     "univpll_d3_d8",
0404     "univpll_d5_d4",
0405     "mainpll_d7_d2"
0406 };
0407
0408 static const char * const nna_parents[] = {
0409     "clk26m",
0410     "univpll_d3_d8",
0411     "mainpll_d2_d4",
0412     "univpll_d3_d2",
0413     "mainpll_d2_d2",
0414     "univpll_d2_d2",
0415     "mainpll_d3",
0416     "univpll_d3",
0417     "mmpll",
0418     "mainpll_d2",
0419     "univpll_d2",
0420     "nnapll_d2",
0421     "nnapll_d4",
0422     "nnapll_d8",
0423     "nnapll",
0424     "nna2pll"
0425 };
0426
0427 static const char * const nna2_parents[] = {
0428     "clk26m",
0429     "univpll_d3_d8",
0430     "mainpll_d2_d4",
0431     "univpll_d3_d2",
0432     "mainpll_d2_d2",
0433     "univpll_d2_d2",
0434     "mainpll_d3",
0435     "univpll_d3",
0436     "mmpll",
0437     "mainpll_d2",
0438     "univpll_d2",
0439     "nna2pll_d2",
0440     "nna2pll_d4",
0441     "nna2pll_d8",
0442     "nnapll",
0443     "nna2pll"
0444 };
0445
0446 static const char * const ssusb_parents[] = {
0447     "clk26m",
0448     "univpll_d5_d4",
0449     "univpll_d5_d2"
0450 };
0451
0452 static const char * const wpe_parents[] = {
0453     "clk26m",
0454     "univpll_d3_d2",
0455     "mainpll_d5",
0456     "univpll_d5",
0457     "univpll_d2_d2",
0458     "mainpll_d3",
0459     "univpll_d3",
0460     "mainpll_d2",
0461     "mmpll"
0462 };
0463
0464 static const char * const dpi_parents[] = {
0465     "clk26m",
0466     "tvdpll",
0467     "tvdpll_d2",
0468     "tvdpll_d4",
0469     "tvdpll_d8",
0470     "tvdpll_d16",
0471     "tvdpll_d32"
0472 };
0473
0474 static const char * const u3_occ_250m_parents[] = {
0475     "clk26m",
0476     "univpll_d5"
0477 };
0478
0479 static const char * const u3_occ_500m_parents[] = {
0480     "clk26m",
0481     "nna2pll_d2"
0482 };
0483
0484 static const char * const adsp_bus_parents[] = {
0485     "clk26m",
0486     "ulposc1_d2",
0487     "mainpll_d5",
0488     "mainpll_d2_d2",
0489     "mainpll_d3",
0490     "mainpll_d2",
0491     "univpll_d3"
0492 };
0493
0494 static const char * const apll_mck_parents[] = {
0495     "top_aud_1",
0496     "top_aud_2"
0497 };
0498
0499 static const struct mtk_mux top_mtk_muxes[] = {
0500     /*
0501      * CLK_CFG_0
0502      * top_axi is bus clock, should not be closed by Linux.
0503      * top_scp is main clock in always-on co-processor.
0504      */
0505     MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "top_axi", axi_parents,
0506                    0x0040, 0x0044, 0x0048, 0, 2, 7, 0x0004, 0,
0507                    CLK_IS_CRITICAL),
0508     MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SCP, "top_scp", scp_parents,
0509                    0x0040, 0x0044, 0x0048, 8, 3, 15, 0x0004, 1,
0510                    CLK_IS_CRITICAL),
0511     MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG, "top_mfg",
0512         mfg_parents, 0x0040, 0x0044, 0x0048, 16, 2, 23, 0x0004, 2),
0513     MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "top_camtg",
0514         camtg_parents, 0x0040, 0x0044, 0x0048, 24, 3, 31, 0x0004, 3),
0515     /* CLK_CFG_1 */
0516     MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG1, "top_camtg1",
0517         camtg_parents, 0x0050, 0x0054, 0x0058, 0, 3, 7, 0x0004, 4),
0518     MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "top_camtg2",
0519         camtg_parents, 0x0050, 0x0054, 0x0058, 8, 3, 15, 0x0004, 5),
0520     MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "top_camtg3",
0521         camtg_parents, 0x0050, 0x0054, 0x0058, 16, 3, 23, 0x0004, 6),
0522     MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4, "top_camtg4",
0523         camtg_parents, 0x0050, 0x0054, 0x0058, 24, 3, 31, 0x0004, 7),
0524     /* CLK_CFG_2 */
0525     MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5, "top_camtg5",
0526         camtg_parents, 0x0060, 0x0064, 0x0068, 0, 3, 7, 0x0004, 8),
0527     MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG6, "top_camtg6",
0528         camtg_parents, 0x0060, 0x0064, 0x0068, 8, 3, 15, 0x0004, 9),
0529     MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "top_uart",
0530         uart_parents, 0x0060, 0x0064, 0x0068, 16, 1, 23, 0x0004, 10),
0531     MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "top_spi",
0532         spi_parents, 0x0060, 0x0064, 0x0068, 24, 3, 31, 0x0004, 11),
0533     /* CLK_CFG_3 */
0534     MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "top_msdc5hclk",
0535         msdc5hclk_parents, 0x0070, 0x0074, 0x0078, 0, 2, 7, 0x0004, 12),
0536     MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "top_msdc50_0",
0537         msdc50_0_parents, 0x0070, 0x0074, 0x0078, 8, 3, 15, 0x0004, 13),
0538     MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "top_msdc30_1",
0539         msdc30_1_parents, 0x0070, 0x0074, 0x0078, 16, 3, 23, 0x0004, 14),
0540     MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO, "top_audio",
0541         audio_parents, 0x0070, 0x0074, 0x0078, 24, 2, 31, 0x0004, 15),
0542     /* CLK_CFG_4 */
0543     MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "top_aud_intbus",
0544         aud_intbus_parents, 0x0080, 0x0084, 0x0088, 0, 2, 7, 0x0004, 16),
0545     MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1, "top_aud_1",
0546         aud_1_parents, 0x0080, 0x0084, 0x0088, 8, 1, 15, 0x0004, 17),
0547     MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2, "top_aud_2",
0548         aud_2_parents, 0x0080, 0x0084, 0x0088, 16, 1, 23, 0x0004, 18),
0549     MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1, "top_aud_engen1",
0550         aud_engen1_parents, 0x0080, 0x0084, 0x0088, 24, 2, 31, 0x0004, 19),
0551     /*
0552      * CLK_CFG_5
0553      * top_sspm is main clock in always-on co-processor, should not be closed
0554      * in Linux.
0555      */
0556     MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2, "top_aud_engen2",
0557         aud_engen2_parents, 0x0090, 0x0094, 0x0098, 0, 2, 7, 0x0004, 20),
0558     MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM, "top_disp_pwm",
0559         disp_pwm_parents, 0x0090, 0x0094, 0x0098, 8, 3, 15, 0x0004, 21),
0560     MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SSPM, "top_sspm", sspm_parents,
0561                    0x0090, 0x0094, 0x0098, 16, 3, 23, 0x0004, 22,
0562                    CLK_IS_CRITICAL),
0563     MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC, "top_dxcc",
0564         dxcc_parents, 0x0090, 0x0094, 0x0098, 24, 2, 31, 0x0004, 23),
0565     /*
0566      * CLK_CFG_6
0567      * top_spm and top_srck are main clocks in always-on co-processor.
0568      */
0569     MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "top_usb",
0570         usb_parents, 0x00a0, 0x00a4, 0x00a8, 0, 2, 7, 0x0004, 24),
0571     MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SRCK, "top_srck", srck_parents,
0572                    0x00a0, 0x00a4, 0x00a8, 8, 2, 15, 0x0004, 25,
0573                    CLK_IS_CRITICAL),
0574     MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "top_spm", spm_parents,
0575                    0x00a0, 0x00a4, 0x00a8, 16, 2, 23, 0x0004, 26,
0576                    CLK_IS_CRITICAL),
0577     MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "top_i2c",
0578         i2c_parents, 0x00a0, 0x00a4, 0x00a8, 24, 2, 31, 0x0004, 27),
0579     /* CLK_CFG_7 */
0580     MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "top_pwm",
0581         pwm_parents, 0x00b0, 0x00b4, 0x00b8, 0, 2, 7, 0x0004, 28),
0582     MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF, "top_seninf",
0583         seninf_parents, 0x00b0, 0x00b4, 0x00b8, 8, 2, 15, 0x0004, 29),
0584     MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "top_seninf1",
0585         seninf_parents, 0x00b0, 0x00b4, 0x00b8, 16, 2, 23, 0x0004, 30),
0586     MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2, "top_seninf2",
0587         seninf_parents, 0x00b0, 0x00b4, 0x00b8, 24, 2, 31, 0x0008, 0),
0588     /* CLK_CFG_8 */
0589     MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF3, "top_seninf3",
0590         seninf_parents, 0x00c0, 0x00c4, 0x00c8, 0, 2, 7, 0x0008, 1),
0591     MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE, "top_aes_msdcfde",
0592         aes_msdcfde_parents, 0x00c0, 0x00c4, 0x00c8, 8, 3, 15, 0x0008, 2),
0593     MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC, "top_pwrap_ulposc",
0594         pwrap_ulposc_parents, 0x00c0, 0x00c4, 0x00c8, 16, 3, 23, 0x0008, 3),
0595     MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "top_camtm",
0596         camtm_parents, 0x00c0, 0x00c4, 0x00c8, 24, 2, 31, 0x0008, 4),
0597     /* CLK_CFG_9 */
0598     MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC, "top_venc",
0599         venc_parents, 0x00d0, 0x00d4, 0x00d8, 0, 3, 7, 0x0008, 5),
0600     MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "top_cam",
0601         isp_parents, 0x00d0, 0x00d4, 0x00d8, 8, 4, 15, 0x0008, 6),
0602     MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG1, "top_img1",
0603         isp_parents, 0x00d0, 0x00d4, 0x00d8, 16, 4, 23, 0x0008, 7),
0604     MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "top_ipe",
0605         isp_parents, 0x00d0, 0x00d4, 0x00d8, 24, 4, 31, 0x0008, 8),
0606     /* CLK_CFG_10 */
0607     MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF, "top_dpmaif",
0608         dpmaif_parents, 0x00e0, 0x00e4, 0x00e8, 0, 3, 7, 0x0008, 9),
0609     MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC, "top_vdec",
0610         vdec_parents, 0x00e0, 0x00e4, 0x00e8, 8, 3, 15, 0x0008, 10),
0611     MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP, "top_disp",
0612         disp_parents, 0x00e0, 0x00e4, 0x00e8, 16, 4, 23, 0x0008, 11),
0613     MUX_GATE_CLR_SET_UPD(CLK_TOP_MDP, "top_mdp",
0614         mdp_parents, 0x00e0, 0x00e4, 0x00e8, 24, 4, 31, 0x0008, 12),
0615     /* CLK_CFG_11 */
0616     MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H, "top_audio_h",
0617         audio_h_parents, 0x00ec, 0x00f0, 0x00f4, 0, 2, 7, 0x0008, 13),
0618     MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS, "top_ufs",
0619         ufs_parents, 0x00ec, 0x00f0, 0x00f4, 8, 2, 15, 0x0008, 14),
0620     MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_FDE, "top_aes_fde",
0621         aes_fde_parents, 0x00ec, 0x00f0, 0x00f4, 16, 2, 23, 0x0008, 15),
0622     MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIODSP, "top_audiodsp",
0623         audiodsp_parents, 0x00ec, 0x00f0, 0x00f4, 24, 3, 31, 0x0008, 16),
0624     /*
0625      * CLK_CFG_12
0626      * dvfsrc is for internal DVFS usage, should not be closed in Linux.
0627      */
0628     MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DVFSRC, "top_dvfsrc", dvfsrc_parents,
0629                    0x0100, 0x0104, 0x0108, 0, 1, 7, 0x0008, 17,
0630                    CLK_IS_CRITICAL),
0631     MUX_GATE_CLR_SET_UPD(CLK_TOP_DSI_OCC, "top_dsi_occ",
0632         dsi_occ_parents, 0x0100, 0x0104, 0x0108, 8, 2, 15, 0x0008, 18),
0633     MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_MST, "top_spmi_mst",
0634         spmi_mst_parents, 0x0100, 0x0104, 0x0108, 16, 3, 23, 0x0008, 19),
0635     /* CLK_CFG_13 */
0636     MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINOR, "top_spinor",
0637         spinor_parents, 0x0110, 0x0114, 0x0118, 0, 3, 6, 0x0008, 20),
0638     MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA, "top_nna",
0639         nna_parents, 0x0110, 0x0114, 0x0118, 7, 4, 14, 0x0008, 21),
0640     MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA1, "top_nna1",
0641         nna_parents, 0x0110, 0x0114, 0x0118, 15, 4, 22, 0x0008, 22),
0642     MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA2, "top_nna2",
0643         nna2_parents, 0x0110, 0x0114, 0x0118, 23, 4, 30, 0x0008, 23),
0644     /* CLK_CFG_14 */
0645     MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI, "top_ssusb_xhci",
0646         ssusb_parents, 0x0120, 0x0124, 0x0128, 0, 2, 5, 0x0008, 24),
0647     MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_TOP_1P, "top_ssusb_1p",
0648         ssusb_parents, 0x0120, 0x0124, 0x0128, 6, 2, 11, 0x0008, 25),
0649     MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_1P, "top_ssusb_xhci_1p",
0650         ssusb_parents, 0x0120, 0x0124, 0x0128, 12, 2, 17, 0x0008, 26),
0651     MUX_GATE_CLR_SET_UPD(CLK_TOP_WPE, "top_wpe",
0652         wpe_parents, 0x0120, 0x0124, 0x0128, 18, 4, 25, 0x0008, 27),
0653     /* CLK_CFG_15 */
0654     MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI, "top_dpi",
0655         dpi_parents, 0x0180, 0x0184, 0x0188, 0, 3, 6, 0x0008, 28),
0656     MUX_GATE_CLR_SET_UPD(CLK_TOP_U3_OCC_250M, "top_u3_occ_250m",
0657         u3_occ_250m_parents, 0x0180, 0x0184, 0x0188, 7, 1, 11, 0x0008, 29),
0658     MUX_GATE_CLR_SET_UPD(CLK_TOP_U3_OCC_500M, "top_u3_occ_500m",
0659         u3_occ_500m_parents, 0x0180, 0x0184, 0x0188, 12, 1, 16, 0x0008, 30),
0660     MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP_BUS, "top_adsp_bus",
0661         adsp_bus_parents, 0x0180, 0x0184, 0x0188, 17, 3, 23, 0x0008, 31),
0662 };
0663
0664 static struct mtk_composite top_muxes[] = {
0665     /* CLK_AUDDIV_0 */
0666     MUX(CLK_TOP_APLL_I2S0_MCK_SEL, "apll_i2s0_mck_sel", apll_mck_parents, 0x0320, 16, 1),
0667     MUX(CLK_TOP_APLL_I2S1_MCK_SEL, "apll_i2s1_mck_sel", apll_mck_parents, 0x0320, 17, 1),
0668     MUX(CLK_TOP_APLL_I2S2_MCK_SEL, "apll_i2s2_mck_sel", apll_mck_parents, 0x0320, 18, 1),
0669     MUX(CLK_TOP_APLL_I2S4_MCK_SEL, "apll_i2s4_mck_sel", apll_mck_parents, 0x0320, 19, 1),
0670     MUX(CLK_TOP_APLL_TDMOUT_MCK_SEL, "apll_tdmout_mck_sel", apll_mck_parents,
0671         0x0320, 20, 1),
0672 };
0673
0674 static const struct mtk_composite top_adj_divs[] = {
0675     DIV_GATE(CLK_TOP_APLL12_CK_DIV0, "apll12_div0", "apll_i2s0_mck_sel",
0676             0x0320, 0, 0x0328, 8, 0),
0677     DIV_GATE(CLK_TOP_APLL12_CK_DIV1, "apll12_div1", "apll_i2s1_mck_sel",
0678             0x0320, 1, 0x0328, 8, 8),
0679     DIV_GATE(CLK_TOP_APLL12_CK_DIV2, "apll12_div2", "apll_i2s2_mck_sel",
0680             0x0320, 2, 0x0328, 8, 16),
0681     DIV_GATE(CLK_TOP_APLL12_CK_DIV4, "apll12_div4", "apll_i2s4_mck_sel",
0682             0x0320, 3, 0x0328, 8, 24),
0683     DIV_GATE(CLK_TOP_APLL12_CK_DIV_TDMOUT_M, "apll12_div_tdmout_m", "apll_tdmout_mck_sel",
0684             0x0320, 4, 0x0334, 8, 0),
0685 };
0686
0687 static const struct of_device_id of_match_clk_mt8186_topck[] = {
0688     { .compatible = "mediatek,mt8186-topckgen", },
0689     {}
0690 };
0691
0692 static int clk_mt8186_topck_probe(struct platform_device *pdev)
0693 {
0694     struct clk_hw_onecell_data *clk_data;
0695     struct device_node *node = pdev->dev.of_node;
0696     int r;
0697     void __iomem *base;
0698
0699     clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
0700     if (!clk_data)
0701         return -ENOMEM;
0702
0703     base = devm_platform_ioremap_resource(pdev, 0);
0704     if (IS_ERR(base)) {
0705         r = PTR_ERR(base);
0706         goto free_top_data;
0707     }
0708
0709     r = mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
0710                     clk_data);
0711     if (r)
0712         goto free_top_data;
0713
0714     r = mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
0715     if (r)
0716         goto unregister_fixed_clks;
0717
0718     r = mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), node,
0719                    &mt8186_clk_lock, clk_data);
0720     if (r)
0721         goto unregister_factors;
0722
0723     r = mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
0724                     &mt8186_clk_lock, clk_data);
0725     if (r)
0726         goto unregister_muxes;
0727
0728     r = mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
0729                     &mt8186_clk_lock, clk_data);
0730     if (r)
0731         goto unregister_composite_muxes;
0732
0733     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0734     if (r)
0735         goto unregister_composite_divs;
0736
0737     platform_set_drvdata(pdev, clk_data);
0738
0739     return r;
0740
0741 unregister_composite_divs:
0742     mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), clk_data);
0743 unregister_composite_muxes:
0744     mtk_clk_unregister_composites(top_muxes, ARRAY_SIZE(top_muxes), clk_data);
0745 unregister_muxes:
0746     mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), clk_data);
0747 unregister_factors:
0748     mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
0749 unregister_fixed_clks:
0750     mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), clk_data);
0751 free_top_data:
0752     mtk_free_clk_data(clk_data);
0753     return r;
0754 }
0755
0756 static int clk_mt8186_topck_remove(struct platform_device *pdev)
0757 {
0758     struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
0759     struct device_node *node = pdev->dev.of_node;
0760
0761     of_clk_del_provider(node);
0762     mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), clk_data);
0763     mtk_clk_unregister_composites(top_muxes, ARRAY_SIZE(top_muxes), clk_data);
0764     mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), clk_data);
0765     mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
0766     mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), clk_data);
0767     mtk_free_clk_data(clk_data);
0768
0769     return 0;
0770 }
0771
0772 static struct platform_driver clk_mt8186_topck_drv = {
0773     .probe = clk_mt8186_topck_probe,
0774     .remove = clk_mt8186_topck_remove,
0775     .driver = {
0776         .name = "clk-mt8186-topck",
0777         .of_match_table = of_match_clk_mt8186_topck,
0778     },
0779 };
0780 builtin_platform_driver(clk_mt8186_topck_drv);