clk/mediatek/clk-mt8186-mdp.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // Copyright (c) 2022 MediaTek Inc.
0004 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
0005
0006 #include <linux/clk-provider.h>
0007 #include <linux/platform_device.h>
0008 #include <dt-bindings/clock/mt8186-clk.h>
0009
0010 #include "clk-gate.h"
0011 #include "clk-mtk.h"
0012
0013 static const struct mtk_gate_regs mdp0_cg_regs = {
0014     .set_ofs = 0x104,
0015     .clr_ofs = 0x108,
0016     .sta_ofs = 0x100,
0017 };
0018
0019 static const struct mtk_gate_regs mdp2_cg_regs = {
0020     .set_ofs = 0x124,
0021     .clr_ofs = 0x128,
0022     .sta_ofs = 0x120,
0023 };
0024
0025 #define GATE_MDP0(_id, _name, _parent, _shift)          \
0026     GATE_MTK(_id, _name, _parent, &mdp0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
0027
0028 #define GATE_MDP2(_id, _name, _parent, _shift)          \
0029     GATE_MTK(_id, _name, _parent, &mdp2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
0030
0031 static const struct mtk_gate mdp_clks[] = {
0032     /* MDP0 */
0033     GATE_MDP0(CLK_MDP_RDMA0, "mdp_rdma0", "top_mdp", 0),
0034     GATE_MDP0(CLK_MDP_TDSHP0, "mdp_tdshp0", "top_mdp", 1),
0035     GATE_MDP0(CLK_MDP_IMG_DL_ASYNC0, "mdp_img_dl_async0", "top_mdp", 2),
0036     GATE_MDP0(CLK_MDP_IMG_DL_ASYNC1, "mdp_img_dl_async1", "top_mdp", 3),
0037     GATE_MDP0(CLK_MDP_DISP_RDMA, "mdp_disp_rdma", "top_mdp", 4),
0038     GATE_MDP0(CLK_MDP_HMS, "mdp_hms", "top_mdp", 5),
0039     GATE_MDP0(CLK_MDP_SMI0, "mdp_smi0", "top_mdp", 6),
0040     GATE_MDP0(CLK_MDP_APB_BUS, "mdp_apb_bus", "top_mdp", 7),
0041     GATE_MDP0(CLK_MDP_WROT0, "mdp_wrot0", "top_mdp", 8),
0042     GATE_MDP0(CLK_MDP_RSZ0, "mdp_rsz0", "top_mdp", 9),
0043     GATE_MDP0(CLK_MDP_HDR0, "mdp_hdr0", "top_mdp", 10),
0044     GATE_MDP0(CLK_MDP_MUTEX0, "mdp_mutex0", "top_mdp", 11),
0045     GATE_MDP0(CLK_MDP_WROT1, "mdp_wrot1", "top_mdp", 12),
0046     GATE_MDP0(CLK_MDP_RSZ1, "mdp_rsz1", "top_mdp", 13),
0047     GATE_MDP0(CLK_MDP_FAKE_ENG0, "mdp_fake_eng0", "top_mdp", 14),
0048     GATE_MDP0(CLK_MDP_AAL0, "mdp_aal0", "top_mdp", 15),
0049     GATE_MDP0(CLK_MDP_DISP_WDMA, "mdp_disp_wdma", "top_mdp", 16),
0050     GATE_MDP0(CLK_MDP_COLOR, "mdp_color", "top_mdp", 17),
0051     GATE_MDP0(CLK_MDP_IMG_DL_ASYNC2, "mdp_img_dl_async2", "top_mdp", 18),
0052     /* MDP2 */
0053     GATE_MDP2(CLK_MDP_IMG_DL_RELAY0_ASYNC0, "mdp_img_dl_rel0_as0", "top_mdp", 0),
0054     GATE_MDP2(CLK_MDP_IMG_DL_RELAY1_ASYNC1, "mdp_img_dl_rel1_as1", "top_mdp", 8),
0055     GATE_MDP2(CLK_MDP_IMG_DL_RELAY2_ASYNC2, "mdp_img_dl_rel2_as2", "top_mdp", 24),
0056 };
0057
0058 static const struct mtk_clk_desc mdp_desc = {
0059     .clks = mdp_clks,
0060     .num_clks = ARRAY_SIZE(mdp_clks),
0061 };
0062
0063 static const struct of_device_id of_match_clk_mt8186_mdp[] = {
0064     {
0065         .compatible = "mediatek,mt8186-mdpsys",
0066         .data = &mdp_desc,
0067     }, {
0068         /* sentinel */
0069     }
0070 };
0071
0072 static struct platform_driver clk_mt8186_mdp_drv = {
0073     .probe = mtk_clk_simple_probe,
0074     .remove = mtk_clk_simple_remove,
0075     .driver = {
0076         .name = "clk-mt8186-mdp",
0077         .of_match_table = of_match_clk_mt8186_mdp,
0078     },
0079 };
0080 builtin_platform_driver(clk_mt8186_mdp_drv);