clk/mediatek/clk-mt8186-infra_ao.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // Copyright (c) 2022 MediaTek Inc.
0004 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
0005
0006 #include <linux/clk-provider.h>
0007 #include <linux/platform_device.h>
0008 #include <dt-bindings/clock/mt8186-clk.h>
0009 #include <dt-bindings/reset/mt8186-resets.h>
0010
0011 #include "clk-gate.h"
0012 #include "clk-mtk.h"
0013
0014 static const struct mtk_gate_regs infra_ao0_cg_regs = {
0015     .set_ofs = 0x80,
0016     .clr_ofs = 0x84,
0017     .sta_ofs = 0x90,
0018 };
0019
0020 static const struct mtk_gate_regs infra_ao1_cg_regs = {
0021     .set_ofs = 0x88,
0022     .clr_ofs = 0x8c,
0023     .sta_ofs = 0x94,
0024 };
0025
0026 static const struct mtk_gate_regs infra_ao2_cg_regs = {
0027     .set_ofs = 0xa4,
0028     .clr_ofs = 0xa8,
0029     .sta_ofs = 0xac,
0030 };
0031
0032 static const struct mtk_gate_regs infra_ao3_cg_regs = {
0033     .set_ofs = 0xc0,
0034     .clr_ofs = 0xc4,
0035     .sta_ofs = 0xc8,
0036 };
0037
0038 #define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag)    \
0039     GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
0040         &mtk_clk_gate_ops_setclr, _flag)
0041
0042 #define GATE_INFRA_AO0(_id, _name, _parent, _shift)         \
0043     GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
0044
0045 #define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag)    \
0046     GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
0047         &mtk_clk_gate_ops_setclr, _flag)
0048
0049 #define GATE_INFRA_AO1(_id, _name, _parent, _shift)         \
0050     GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
0051
0052 #define GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, _flag)    \
0053     GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao2_cg_regs, _shift, \
0054         &mtk_clk_gate_ops_setclr, _flag)
0055
0056 #define GATE_INFRA_AO2(_id, _name, _parent, _shift)         \
0057     GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, 0)
0058
0059  #define GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, _flag)        \
0060     GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao3_cg_regs, _shift, \
0061         &mtk_clk_gate_ops_setclr, _flag)
0062
0063 #define GATE_INFRA_AO3(_id, _name, _parent, _shift)         \
0064     GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, 0)
0065
0066 static const struct mtk_gate infra_ao_clks[] = {
0067     /* INFRA_AO0 */
0068     GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_TMR, "infra_ao_pmic_tmr", "top_pwrap_ulposc", 0),
0069     GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_AP, "infra_ao_pmic_ap", "top_pwrap_ulposc", 1),
0070     GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_MD, "infra_ao_pmic_md", "top_pwrap_ulposc", 2),
0071     GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_CONN, "infra_ao_pmic_conn", "top_pwrap_ulposc", 3),
0072     /* infra_ao_scp_core are main clock in always-on co-processor. */
0073     GATE_INFRA_AO0_FLAGS(CLK_INFRA_AO_SCP_CORE,
0074                  "infra_ao_scp_core", "top_scp", 4, CLK_IS_CRITICAL),
0075     /* infra_ao_sej is main clock for secure engine with JTAG support */
0076     GATE_INFRA_AO0_FLAGS(CLK_INFRA_AO_SEJ,
0077                  "infra_ao_sej", "top_axi", 5, CLK_IS_CRITICAL),
0078     GATE_INFRA_AO0(CLK_INFRA_AO_APXGPT, "infra_ao_apxgpt", "top_axi", 6),
0079     GATE_INFRA_AO0(CLK_INFRA_AO_ICUSB, "infra_ao_icusb", "top_axi", 8),
0080     GATE_INFRA_AO0(CLK_INFRA_AO_GCE, "infra_ao_gce", "top_axi", 9),
0081     GATE_INFRA_AO0(CLK_INFRA_AO_THERM, "infra_ao_therm", "top_axi", 10),
0082     GATE_INFRA_AO0(CLK_INFRA_AO_I2C_AP, "infra_ao_i2c_ap", "top_i2c", 11),
0083     GATE_INFRA_AO0(CLK_INFRA_AO_I2C_CCU, "infra_ao_i2c_ccu", "top_i2c", 12),
0084     GATE_INFRA_AO0(CLK_INFRA_AO_I2C_SSPM, "infra_ao_i2c_sspm", "top_i2c", 13),
0085     GATE_INFRA_AO0(CLK_INFRA_AO_I2C_RSV, "infra_ao_i2c_rsv", "top_i2c", 14),
0086     GATE_INFRA_AO0(CLK_INFRA_AO_PWM_HCLK, "infra_ao_pwm_hclk", "top_axi", 15),
0087     GATE_INFRA_AO0(CLK_INFRA_AO_PWM1, "infra_ao_pwm1", "top_pwm", 16),
0088     GATE_INFRA_AO0(CLK_INFRA_AO_PWM2, "infra_ao_pwm2", "top_pwm", 17),
0089     GATE_INFRA_AO0(CLK_INFRA_AO_PWM3, "infra_ao_pwm3", "top_pwm", 18),
0090     GATE_INFRA_AO0(CLK_INFRA_AO_PWM4, "infra_ao_pwm4", "top_pwm", 19),
0091     GATE_INFRA_AO0(CLK_INFRA_AO_PWM5, "infra_ao_pwm5", "top_pwm", 20),
0092     GATE_INFRA_AO0(CLK_INFRA_AO_PWM, "infra_ao_pwm", "top_pwm", 21),
0093     GATE_INFRA_AO0(CLK_INFRA_AO_UART0, "infra_ao_uart0", "top_uart", 22),
0094     GATE_INFRA_AO0(CLK_INFRA_AO_UART1, "infra_ao_uart1", "top_uart", 23),
0095     GATE_INFRA_AO0(CLK_INFRA_AO_UART2, "infra_ao_uart2", "top_uart", 24),
0096     GATE_INFRA_AO0(CLK_INFRA_AO_GCE_26M, "infra_ao_gce_26m", "clk26m", 27),
0097     GATE_INFRA_AO0(CLK_INFRA_AO_CQ_DMA_FPC, "infra_ao_dma", "top_axi", 28),
0098     GATE_INFRA_AO0(CLK_INFRA_AO_BTIF, "infra_ao_btif", "top_axi", 31),
0099     /* INFRA_AO1 */
0100     GATE_INFRA_AO1(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "top_spi", 1),
0101     GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0, "infra_ao_msdc0", "top_msdc5hclk", 2),
0102     GATE_INFRA_AO1(CLK_INFRA_AO_MSDCFDE, "infra_ao_msdcfde", "top_aes_msdcfde", 3),
0103     GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1, "infra_ao_msdc1", "top_axi", 4),
0104     /* infra_ao_dvfsrc is for internal DVFS usage, should not be handled by Linux */
0105     GATE_INFRA_AO1_FLAGS(CLK_INFRA_AO_DVFSRC,
0106                  "infra_ao_dvfsrc", "top_dvfsrc", 7, CLK_IS_CRITICAL),
0107     GATE_INFRA_AO1(CLK_INFRA_AO_GCPU, "infra_ao_gcpu", "top_axi", 8),
0108     GATE_INFRA_AO1(CLK_INFRA_AO_TRNG, "infra_ao_trng", "top_axi", 9),
0109     GATE_INFRA_AO1(CLK_INFRA_AO_AUXADC, "infra_ao_auxadc", "clk26m", 10),
0110     GATE_INFRA_AO1(CLK_INFRA_AO_CPUM, "infra_ao_cpum", "top_axi", 11),
0111     GATE_INFRA_AO1(CLK_INFRA_AO_CCIF1_AP, "infra_ao_ccif1_ap", "top_axi", 12),
0112     GATE_INFRA_AO1(CLK_INFRA_AO_CCIF1_MD, "infra_ao_ccif1_md", "top_axi", 13),
0113     GATE_INFRA_AO1(CLK_INFRA_AO_AUXADC_MD, "infra_ao_auxadc_md", "clk26m", 14),
0114     GATE_INFRA_AO1(CLK_INFRA_AO_AP_DMA, "infra_ao_ap_dma", "top_axi", 18),
0115     GATE_INFRA_AO1(CLK_INFRA_AO_XIU, "infra_ao_xiu", "top_axi", 19),
0116     /* infra_ao_device_apc is for device access permission control module */
0117     GATE_INFRA_AO1_FLAGS(CLK_INFRA_AO_DEVICE_APC,
0118                  "infra_ao_dapc", "top_axi", 20, CLK_IS_CRITICAL),
0119     GATE_INFRA_AO1(CLK_INFRA_AO_CCIF_AP, "infra_ao_ccif_ap", "top_axi", 23),
0120     GATE_INFRA_AO1(CLK_INFRA_AO_DEBUGTOP, "infra_ao_debugtop", "top_axi", 24),
0121     GATE_INFRA_AO1(CLK_INFRA_AO_AUDIO, "infra_ao_audio", "top_axi", 25),
0122     GATE_INFRA_AO1(CLK_INFRA_AO_CCIF_MD, "infra_ao_ccif_md", "top_axi", 26),
0123     GATE_INFRA_AO1(CLK_INFRA_AO_DXCC_SEC_CORE, "infra_ao_secore", "top_dxcc", 27),
0124     GATE_INFRA_AO1(CLK_INFRA_AO_DXCC_AO, "infra_ao_dxcc_ao", "top_dxcc", 28),
0125     GATE_INFRA_AO1(CLK_INFRA_AO_IMP_IIC, "infra_ao_imp_iic", "top_axi", 29),
0126     GATE_INFRA_AO1(CLK_INFRA_AO_DRAMC_F26M, "infra_ao_dramc26", "clk26m", 31),
0127     /* INFRA_AO2 */
0128     GATE_INFRA_AO2(CLK_INFRA_AO_RG_PWM_FBCLK6, "infra_ao_pwm_fbclk6", "clk26m", 0),
0129     GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_TOP_HCLK, "infra_ao_ssusb_hclk", "top_axi", 1),
0130     GATE_INFRA_AO2(CLK_INFRA_AO_DISP_PWM, "infra_ao_disp_pwm", "top_disp_pwm", 2),
0131     GATE_INFRA_AO2(CLK_INFRA_AO_CLDMA_BCLK, "infra_ao_cldmabclk", "top_axi", 3),
0132     GATE_INFRA_AO2(CLK_INFRA_AO_AUDIO_26M_BCLK, "infra_ao_audio26m", "clk26m", 4),
0133     GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_TOP_P1_HCLK, "infra_ao_ssusb_p1_hclk", "top_axi", 5),
0134     GATE_INFRA_AO2(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "top_spi", 6),
0135     GATE_INFRA_AO2(CLK_INFRA_AO_I2C4, "infra_ao_i2c4", "top_i2c", 7),
0136     GATE_INFRA_AO2(CLK_INFRA_AO_MODEM_TEMP_SHARE, "infra_ao_mdtemp", "clk26m", 8),
0137     GATE_INFRA_AO2(CLK_INFRA_AO_SPI2, "infra_ao_spi2", "top_spi", 9),
0138     GATE_INFRA_AO2(CLK_INFRA_AO_SPI3, "infra_ao_spi3", "top_spi", 10),
0139     GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_TOP_REF, "infra_ao_ssusb_ref", "clk26m", 11),
0140     GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_TOP_XHCI, "infra_ao_ssusb_xhci", "top_ssusb_xhci", 12),
0141     GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_TOP_P1_REF, "infra_ao_ssusb_p1_ref", "clk26m", 13),
0142     GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_TOP_P1_XHCI,
0143                "infra_ao_ssusb_p1_xhci", "top_ssusb_xhci_1p", 14),
0144     /* infra_ao_sspm is main clock in co-processor, should not be closed in Linux. */
0145     GATE_INFRA_AO2_FLAGS(CLK_INFRA_AO_SSPM, "infra_ao_sspm", "top_sspm", 15, CLK_IS_CRITICAL),
0146     GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_TOP_P1_SYS,
0147                "infra_ao_ssusb_p1_sys", "top_ssusb_1p", 16),
0148     GATE_INFRA_AO2(CLK_INFRA_AO_I2C5, "infra_ao_i2c5", "top_i2c", 18),
0149     GATE_INFRA_AO2(CLK_INFRA_AO_I2C5_ARBITER, "infra_ao_i2c5a", "top_i2c", 19),
0150     GATE_INFRA_AO2(CLK_INFRA_AO_I2C5_IMM, "infra_ao_i2c5_imm", "top_i2c", 20),
0151     GATE_INFRA_AO2(CLK_INFRA_AO_I2C1_ARBITER, "infra_ao_i2c1a", "top_i2c", 21),
0152     GATE_INFRA_AO2(CLK_INFRA_AO_I2C1_IMM, "infra_ao_i2c1_imm", "top_i2c", 22),
0153     GATE_INFRA_AO2(CLK_INFRA_AO_I2C2_ARBITER, "infra_ao_i2c2a", "top_i2c", 23),
0154     GATE_INFRA_AO2(CLK_INFRA_AO_I2C2_IMM, "infra_ao_i2c2_imm", "top_i2c", 24),
0155     GATE_INFRA_AO2(CLK_INFRA_AO_SPI4, "infra_ao_spi4", "top_spi", 25),
0156     GATE_INFRA_AO2(CLK_INFRA_AO_SPI5, "infra_ao_spi5", "top_spi", 26),
0157     GATE_INFRA_AO2(CLK_INFRA_AO_CQ_DMA, "infra_ao_cq_dma", "top_axi", 27),
0158     GATE_INFRA_AO2(CLK_INFRA_AO_BIST2FPC, "infra_ao_bist2fpc", "f_bist2fpc_ck", 28),
0159     /* INFRA_AO3 */
0160     GATE_INFRA_AO3(CLK_INFRA_AO_MSDC0_SELF, "infra_ao_msdc0sf", "top_msdc50_0", 0),
0161     GATE_INFRA_AO3(CLK_INFRA_AO_SPINOR, "infra_ao_spinor", "top_spinor", 1),
0162     /*
0163      * infra_ao_sspm_26m/infra_ao_sspm_32k are main clocks in co-processor,
0164      * should not be closed in Linux.
0165      */
0166     GATE_INFRA_AO3_FLAGS(CLK_INFRA_AO_SSPM_26M_SELF, "infra_ao_sspm_26m", "clk26m", 3,
0167                  CLK_IS_CRITICAL),
0168     GATE_INFRA_AO3_FLAGS(CLK_INFRA_AO_SSPM_32K_SELF, "infra_ao_sspm_32k", "clk32k", 4,
0169                  CLK_IS_CRITICAL),
0170     GATE_INFRA_AO3(CLK_INFRA_AO_I2C6, "infra_ao_i2c6", "top_i2c", 6),
0171     GATE_INFRA_AO3(CLK_INFRA_AO_AP_MSDC0, "infra_ao_ap_msdc0", "top_axi", 7),
0172     GATE_INFRA_AO3(CLK_INFRA_AO_MD_MSDC0, "infra_ao_md_msdc0", "top_axi", 8),
0173     GATE_INFRA_AO3(CLK_INFRA_AO_MSDC0_SRC, "infra_ao_msdc0_clk", "top_msdc50_0", 9),
0174     GATE_INFRA_AO3(CLK_INFRA_AO_MSDC1_SRC, "infra_ao_msdc1_clk", "top_msdc30_1", 10),
0175     /* infra_ao_sej_f13m is main clock for secure engine with JTAG support */
0176     GATE_INFRA_AO3_FLAGS(CLK_INFRA_AO_SEJ_F13M,
0177                  "infra_ao_sej_f13m", "clk26m", 15, CLK_IS_CRITICAL),
0178     /* infra_ao_aes_top0_bclk is for secure encryption */
0179     GATE_INFRA_AO3_FLAGS(CLK_INFRA_AO_AES_TOP0_BCLK,
0180                  "infra_ao_aes_top0_bclk", "top_axi", 16, CLK_IS_CRITICAL),
0181     GATE_INFRA_AO3(CLK_INFRA_AO_MCU_PM_BCLK, "infra_ao_mcu_pm_bclk", "top_axi", 17),
0182     GATE_INFRA_AO3(CLK_INFRA_AO_CCIF2_AP, "infra_ao_ccif2_ap", "top_axi", 18),
0183     GATE_INFRA_AO3(CLK_INFRA_AO_CCIF2_MD, "infra_ao_ccif2_md", "top_axi", 19),
0184     GATE_INFRA_AO3(CLK_INFRA_AO_CCIF3_AP, "infra_ao_ccif3_ap", "top_axi", 20),
0185     GATE_INFRA_AO3(CLK_INFRA_AO_CCIF3_MD, "infra_ao_ccif3_md", "top_axi", 21),
0186     GATE_INFRA_AO3(CLK_INFRA_AO_FADSP_26M, "infra_ao_fadsp_26m", "clk26m", 22),
0187     GATE_INFRA_AO3(CLK_INFRA_AO_FADSP_32K, "infra_ao_fadsp_32k", "clk32k", 23),
0188     GATE_INFRA_AO3(CLK_INFRA_AO_CCIF4_AP, "infra_ao_ccif4_ap", "top_axi", 24),
0189     GATE_INFRA_AO3(CLK_INFRA_AO_CCIF4_MD, "infra_ao_ccif4_md", "top_axi", 25),
0190     GATE_INFRA_AO3(CLK_INFRA_AO_FADSP, "infra_ao_fadsp", "top_audiodsp", 27),
0191     GATE_INFRA_AO3(CLK_INFRA_AO_FLASHIF_133M, "infra_ao_flashif_133m", "top_axi", 28),
0192     GATE_INFRA_AO3(CLK_INFRA_AO_FLASHIF_66M, "infra_ao_flashif_66m", "top_axi", 29),
0193 };
0194
0195 static u16 infra_ao_rst_ofs[] = {
0196     INFRA_RST0_SET_OFFSET,
0197     INFRA_RST1_SET_OFFSET,
0198     INFRA_RST2_SET_OFFSET,
0199     INFRA_RST3_SET_OFFSET,
0200     INFRA_RST4_SET_OFFSET,
0201 };
0202
0203 static u16 infra_ao_idx_map[] = {
0204     [MT8186_INFRA_THERMAL_CTRL_RST] = 0 * RST_NR_PER_BANK + 0,
0205     [MT8186_INFRA_PTP_CTRL_RST] = 1 * RST_NR_PER_BANK + 0,
0206 };
0207
0208 static struct mtk_clk_rst_desc infra_ao_rst_desc = {
0209     .version = MTK_RST_SET_CLR,
0210     .rst_bank_ofs = infra_ao_rst_ofs,
0211     .rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),
0212     .rst_idx_map = infra_ao_idx_map,
0213     .rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),
0214 };
0215
0216 static const struct mtk_clk_desc infra_ao_desc = {
0217     .clks = infra_ao_clks,
0218     .num_clks = ARRAY_SIZE(infra_ao_clks),
0219     .rst_desc = &infra_ao_rst_desc,
0220 };
0221
0222 static const struct of_device_id of_match_clk_mt8186_infra_ao[] = {
0223     {
0224         .compatible = "mediatek,mt8186-infracfg_ao",
0225         .data = &infra_ao_desc,
0226     }, {
0227         /* sentinel */
0228     }
0229 };
0230
0231 static struct platform_driver clk_mt8186_infra_ao_drv = {
0232     .probe = mtk_clk_simple_probe,
0233     .remove = mtk_clk_simple_remove,
0234     .driver = {
0235         .name = "clk-mt8186-infra-ao",
0236         .of_match_table = of_match_clk_mt8186_infra_ao,
0237     },
0238 };
0239 builtin_platform_driver(clk_mt8186_infra_ao_drv);