clk/mediatek/clk-mt8186-apmixedsys.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // Copyright (c) 2022 MediaTek Inc.
0004 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
0005
0006 #include <linux/clk-provider.h>
0007 #include <linux/platform_device.h>
0008 #include <dt-bindings/clock/mt8186-clk.h>
0009
0010 #include "clk-mtk.h"
0011 #include "clk-pll.h"
0012
0013 #define MT8186_PLL_FMAX     (3800UL * MHZ)
0014 #define MT8186_PLL_FMIN     (1500UL * MHZ)
0015 #define MT8186_INTEGER_BITS (8)
0016
0017 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags,       \
0018         _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift,        \
0019         _tuner_reg, _tuner_en_reg, _tuner_en_bit,           \
0020         _pcw_reg) {                         \
0021         .id = _id,                      \
0022         .name = _name,                      \
0023         .reg = _reg,                        \
0024         .pwr_reg = _pwr_reg,                    \
0025         .en_mask = _en_mask,                    \
0026         .flags = _flags,                    \
0027         .rst_bar_mask = _rst_bar_mask,              \
0028         .fmax = MT8186_PLL_FMAX,                \
0029         .fmin = MT8186_PLL_FMIN,                \
0030         .pcwbits = _pcwbits,                    \
0031         .pcwibits = MT8186_INTEGER_BITS,            \
0032         .pd_reg = _pd_reg,                  \
0033         .pd_shift = _pd_shift,                  \
0034         .tuner_reg = _tuner_reg,                \
0035         .tuner_en_reg = _tuner_en_reg,              \
0036         .tuner_en_bit = _tuner_en_bit,              \
0037         .pcw_reg = _pcw_reg,                    \
0038         .pcw_shift = 0,                     \
0039         .pcw_chg_reg = 0,                   \
0040         .en_reg = 0,                        \
0041         .pll_en_bit = 0,                    \
0042     }
0043
0044 static const struct mtk_pll_data plls[] = {
0045     /*
0046      * armpll_ll/armpll_bl/ccipll are main clock source of AP MCU,
0047      * should not be closed in Linux world.
0048      */
0049     PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0204, 0x0210, 0,
0050         PLL_AO, 0, 22, 0x0208, 24, 0, 0, 0, 0x0208),
0051     PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0214, 0x0220, 0,
0052         PLL_AO, 0, 22, 0x0218, 24, 0, 0, 0, 0x0218),
0053     PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0224, 0x0230, 0,
0054         PLL_AO, 0, 22, 0x0228, 24, 0, 0, 0, 0x0228),
0055     PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0244, 0x0250, 0xff000000,
0056         HAVE_RST_BAR, BIT(23), 22, 0x0248, 24, 0, 0, 0, 0x0248),
0057     PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0324, 0x0330, 0xff000000,
0058         HAVE_RST_BAR, BIT(23), 22, 0x0328, 24, 0, 0, 0, 0x0328),
0059     PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x038C, 0x0398, 0,
0060         0, 0, 22, 0x0390, 24, 0, 0, 0, 0x0390),
0061     PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0254, 0x0260, 0,
0062         0, 0, 22, 0x0258, 24, 0, 0, 0, 0x0258),
0063     PLL(CLK_APMIXED_NNAPLL, "nnapll", 0x035C, 0x0368, 0,
0064         0, 0, 22, 0x0360, 24, 0, 0, 0, 0x0360),
0065     PLL(CLK_APMIXED_NNA2PLL, "nna2pll", 0x036C, 0x0378, 0,
0066         0, 0, 22, 0x0370, 24, 0, 0, 0, 0x0370),
0067     PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x0304, 0x0310, 0,
0068         0, 0, 22, 0x0308, 24, 0, 0, 0, 0x0308),
0069     PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0314, 0x0320, 0,
0070         0, 0, 22, 0x0318, 24, 0, 0, 0, 0x0318),
0071     PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0264, 0x0270, 0,
0072         0, 0, 22, 0x0268, 24, 0, 0, 0, 0x0268),
0073     PLL(CLK_APMIXED_APLL1, "apll1", 0x0334, 0x0344, 0,
0074         0, 0, 32, 0x0338, 24, 0x0040, 0x000C, 0, 0x033C),
0075     PLL(CLK_APMIXED_APLL2, "apll2", 0x0348, 0x0358, 0,
0076         0, 0, 32, 0x034C, 24, 0x0044, 0x000C, 5, 0x0350),
0077 };
0078
0079 static const struct of_device_id of_match_clk_mt8186_apmixed[] = {
0080     { .compatible = "mediatek,mt8186-apmixedsys", },
0081     {}
0082 };
0083
0084 static int clk_mt8186_apmixed_probe(struct platform_device *pdev)
0085 {
0086     struct clk_hw_onecell_data *clk_data;
0087     struct device_node *node = pdev->dev.of_node;
0088     int r;
0089
0090     clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
0091     if (!clk_data)
0092         return -ENOMEM;
0093
0094     r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
0095     if (r)
0096         goto free_apmixed_data;
0097
0098     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0099     if (r)
0100         goto unregister_plls;
0101
0102     platform_set_drvdata(pdev, clk_data);
0103
0104     return r;
0105
0106 unregister_plls:
0107     mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
0108 free_apmixed_data:
0109     mtk_free_clk_data(clk_data);
0110     return r;
0111 }
0112
0113 static int clk_mt8186_apmixed_remove(struct platform_device *pdev)
0114 {
0115     struct device_node *node = pdev->dev.of_node;
0116     struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
0117
0118     of_clk_del_provider(node);
0119     mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
0120     mtk_free_clk_data(clk_data);
0121
0122     return 0;
0123 }
0124
0125 static struct platform_driver clk_mt8186_apmixed_drv = {
0126     .probe = clk_mt8186_apmixed_probe,
0127     .remove = clk_mt8186_apmixed_remove,
0128     .driver = {
0129         .name = "clk-mt8186-apmixed",
0130         .of_match_table = of_match_clk_mt8186_apmixed,
0131     },
0132 };
0133 builtin_platform_driver(clk_mt8186_apmixed_drv);