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0006 #include <linux/clk-provider.h>
0007 #include <linux/platform_device.h>
0008
0009 #include "clk-mtk.h"
0010 #include "clk-gate.h"
0011
0012 #include <dt-bindings/clock/mt8183-clk.h>
0013
0014 static const struct mtk_gate_regs vdec0_cg_regs = {
0015 .set_ofs = 0x0,
0016 .clr_ofs = 0x4,
0017 .sta_ofs = 0x0,
0018 };
0019
0020 static const struct mtk_gate_regs vdec1_cg_regs = {
0021 .set_ofs = 0x8,
0022 .clr_ofs = 0xc,
0023 .sta_ofs = 0x8,
0024 };
0025
0026 #define GATE_VDEC0_I(_id, _name, _parent, _shift) \
0027 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, \
0028 &mtk_clk_gate_ops_setclr_inv)
0029
0030 #define GATE_VDEC1_I(_id, _name, _parent, _shift) \
0031 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, \
0032 &mtk_clk_gate_ops_setclr_inv)
0033
0034 static const struct mtk_gate vdec_clks[] = {
0035
0036 GATE_VDEC0_I(CLK_VDEC_VDEC, "vdec_vdec", "mm_sel", 0),
0037
0038 GATE_VDEC1_I(CLK_VDEC_LARB1, "vdec_larb1", "mm_sel", 0),
0039 };
0040
0041 static int clk_mt8183_vdec_probe(struct platform_device *pdev)
0042 {
0043 struct clk_hw_onecell_data *clk_data;
0044 struct device_node *node = pdev->dev.of_node;
0045
0046 clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
0047
0048 mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
0049 clk_data);
0050
0051 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0052 }
0053
0054 static const struct of_device_id of_match_clk_mt8183_vdec[] = {
0055 { .compatible = "mediatek,mt8183-vdecsys", },
0056 {}
0057 };
0058
0059 static struct platform_driver clk_mt8183_vdec_drv = {
0060 .probe = clk_mt8183_vdec_probe,
0061 .driver = {
0062 .name = "clk-mt8183-vdec",
0063 .of_match_table = of_match_clk_mt8183_vdec,
0064 },
0065 };
0066
0067 builtin_platform_driver(clk_mt8183_vdec_drv);