clk/mediatek/clk-mt8183-mfgcfg.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Copyright (c) 2018 MediaTek Inc.
0004 // Author: Weiyi Lu <weiyi.lu@mediatek.com>
0005
0006 #include <linux/clk-provider.h>
0007 #include <linux/platform_device.h>
0008 #include <linux/pm_runtime.h>
0009
0010 #include "clk-mtk.h"
0011 #include "clk-gate.h"
0012
0013 #include <dt-bindings/clock/mt8183-clk.h>
0014
0015 static const struct mtk_gate_regs mfg_cg_regs = {
0016     .set_ofs = 0x4,
0017     .clr_ofs = 0x8,
0018     .sta_ofs = 0x0,
0019 };
0020
0021 #define GATE_MFG(_id, _name, _parent, _shift)           \
0022     GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, \
0023         &mtk_clk_gate_ops_setclr)
0024
0025 static const struct mtk_gate mfg_clks[] = {
0026     GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0)
0027 };
0028
0029 static int clk_mt8183_mfg_probe(struct platform_device *pdev)
0030 {
0031     struct clk_hw_onecell_data *clk_data;
0032     struct device_node *node = pdev->dev.of_node;
0033
0034     pm_runtime_enable(&pdev->dev);
0035
0036     clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK);
0037
0038     mtk_clk_register_gates_with_dev(node, mfg_clks, ARRAY_SIZE(mfg_clks),
0039             clk_data, &pdev->dev);
0040
0041     return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0042 }
0043
0044 static const struct of_device_id of_match_clk_mt8183_mfg[] = {
0045     { .compatible = "mediatek,mt8183-mfgcfg", },
0046     {}
0047 };
0048
0049 static struct platform_driver clk_mt8183_mfg_drv = {
0050     .probe = clk_mt8183_mfg_probe,
0051     .driver = {
0052         .name = "clk-mt8183-mfg",
0053         .of_match_table = of_match_clk_mt8183_mfg,
0054     },
0055 };
0056
0057 builtin_platform_driver(clk_mt8183_mfg_drv);