clk/mediatek/clk-mt8183-ipu_conn.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Copyright (c) 2018 MediaTek Inc.
0004 // Author: Weiyi Lu <weiyi.lu@mediatek.com>
0005
0006 #include <linux/clk-provider.h>
0007 #include <linux/platform_device.h>
0008
0009 #include "clk-mtk.h"
0010 #include "clk-gate.h"
0011
0012 #include <dt-bindings/clock/mt8183-clk.h>
0013
0014 static const struct mtk_gate_regs ipu_conn_cg_regs = {
0015     .set_ofs = 0x4,
0016     .clr_ofs = 0x8,
0017     .sta_ofs = 0x0,
0018 };
0019
0020 static const struct mtk_gate_regs ipu_conn_apb_cg_regs = {
0021     .set_ofs = 0x10,
0022     .clr_ofs = 0x10,
0023     .sta_ofs = 0x10,
0024 };
0025
0026 static const struct mtk_gate_regs ipu_conn_axi_cg_regs = {
0027     .set_ofs = 0x18,
0028     .clr_ofs = 0x18,
0029     .sta_ofs = 0x18,
0030 };
0031
0032 static const struct mtk_gate_regs ipu_conn_axi1_cg_regs = {
0033     .set_ofs = 0x1c,
0034     .clr_ofs = 0x1c,
0035     .sta_ofs = 0x1c,
0036 };
0037
0038 static const struct mtk_gate_regs ipu_conn_axi2_cg_regs = {
0039     .set_ofs = 0x20,
0040     .clr_ofs = 0x20,
0041     .sta_ofs = 0x20,
0042 };
0043
0044 #define GATE_IPU_CONN(_id, _name, _parent, _shift)          \
0045     GATE_MTK(_id, _name, _parent, &ipu_conn_cg_regs, _shift,    \
0046         &mtk_clk_gate_ops_setclr)
0047
0048 #define GATE_IPU_CONN_APB(_id, _name, _parent, _shift)          \
0049     GATE_MTK(_id, _name, _parent, &ipu_conn_apb_cg_regs, _shift,    \
0050         &mtk_clk_gate_ops_no_setclr)
0051
0052 #define GATE_IPU_CONN_AXI_I(_id, _name, _parent, _shift)        \
0053     GATE_MTK(_id, _name, _parent, &ipu_conn_axi_cg_regs, _shift,    \
0054         &mtk_clk_gate_ops_no_setclr_inv)
0055
0056 #define GATE_IPU_CONN_AXI1_I(_id, _name, _parent, _shift)       \
0057     GATE_MTK(_id, _name, _parent, &ipu_conn_axi1_cg_regs, _shift,   \
0058         &mtk_clk_gate_ops_no_setclr_inv)
0059
0060 #define GATE_IPU_CONN_AXI2_I(_id, _name, _parent, _shift)       \
0061     GATE_MTK(_id, _name, _parent, &ipu_conn_axi2_cg_regs, _shift,   \
0062         &mtk_clk_gate_ops_no_setclr_inv)
0063
0064 static const struct mtk_gate ipu_conn_clks[] = {
0065     GATE_IPU_CONN(CLK_IPU_CONN_IPU,
0066         "ipu_conn_ipu", "dsp_sel", 0),
0067     GATE_IPU_CONN(CLK_IPU_CONN_AHB,
0068         "ipu_conn_ahb", "dsp_sel", 1),
0069     GATE_IPU_CONN(CLK_IPU_CONN_AXI,
0070         "ipu_conn_axi", "dsp_sel", 2),
0071     GATE_IPU_CONN(CLK_IPU_CONN_ISP,
0072         "ipu_conn_isp", "dsp_sel", 3),
0073     GATE_IPU_CONN(CLK_IPU_CONN_CAM_ADL,
0074         "ipu_conn_cam_adl", "dsp_sel", 4),
0075     GATE_IPU_CONN(CLK_IPU_CONN_IMG_ADL,
0076         "ipu_conn_img_adl", "dsp_sel", 5),
0077     GATE_IPU_CONN_APB(CLK_IPU_CONN_DAP_RX,
0078         "ipu_conn_dap_rx", "dsp1_sel", 0),
0079     GATE_IPU_CONN_APB(CLK_IPU_CONN_APB2AXI,
0080         "ipu_conn_apb2axi", "dsp1_sel", 3),
0081     GATE_IPU_CONN_APB(CLK_IPU_CONN_APB2AHB,
0082         "ipu_conn_apb2ahb", "dsp1_sel", 20),
0083     GATE_IPU_CONN_AXI_I(CLK_IPU_CONN_IPU_CAB1TO2,
0084         "ipu_conn_ipu_cab1to2", "dsp1_sel", 6),
0085     GATE_IPU_CONN_AXI_I(CLK_IPU_CONN_IPU1_CAB1TO2,
0086         "ipu_conn_ipu1_cab1to2", "dsp1_sel", 13),
0087     GATE_IPU_CONN_AXI_I(CLK_IPU_CONN_IPU2_CAB1TO2,
0088         "ipu_conn_ipu2_cab1to2", "dsp1_sel", 20),
0089     GATE_IPU_CONN_AXI1_I(CLK_IPU_CONN_CAB3TO3,
0090         "ipu_conn_cab3to3", "dsp1_sel", 0),
0091     GATE_IPU_CONN_AXI2_I(CLK_IPU_CONN_CAB2TO1,
0092         "ipu_conn_cab2to1", "dsp1_sel", 14),
0093     GATE_IPU_CONN_AXI2_I(CLK_IPU_CONN_CAB3TO1_SLICE,
0094         "ipu_conn_cab3to1_slice", "dsp1_sel", 17),
0095 };
0096
0097 static int clk_mt8183_ipu_conn_probe(struct platform_device *pdev)
0098 {
0099     struct clk_hw_onecell_data *clk_data;
0100     struct device_node *node = pdev->dev.of_node;
0101
0102     clk_data = mtk_alloc_clk_data(CLK_IPU_CONN_NR_CLK);
0103
0104     mtk_clk_register_gates(node, ipu_conn_clks, ARRAY_SIZE(ipu_conn_clks),
0105             clk_data);
0106
0107     return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0108 }
0109
0110 static const struct of_device_id of_match_clk_mt8183_ipu_conn[] = {
0111     { .compatible = "mediatek,mt8183-ipu_conn", },
0112     {}
0113 };
0114
0115 static struct platform_driver clk_mt8183_ipu_conn_drv = {
0116     .probe = clk_mt8183_ipu_conn_probe,
0117     .driver = {
0118         .name = "clk-mt8183-ipu_conn",
0119         .of_match_table = of_match_clk_mt8183_ipu_conn,
0120     },
0121 };
0122
0123 builtin_platform_driver(clk_mt8183_ipu_conn_drv);