clk/mediatek/clk-mt8183-ipu_adl.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Copyright (c) 2018 MediaTek Inc.
0004 // Author: Weiyi Lu <weiyi.lu@mediatek.com>
0005
0006 #include <linux/clk-provider.h>
0007 #include <linux/platform_device.h>
0008
0009 #include "clk-mtk.h"
0010 #include "clk-gate.h"
0011
0012 #include <dt-bindings/clock/mt8183-clk.h>
0013
0014 static const struct mtk_gate_regs ipu_adl_cg_regs = {
0015     .set_ofs = 0x204,
0016     .clr_ofs = 0x204,
0017     .sta_ofs = 0x204,
0018 };
0019
0020 #define GATE_IPU_ADL_I(_id, _name, _parent, _shift)     \
0021     GATE_MTK(_id, _name, _parent, &ipu_adl_cg_regs, _shift, \
0022         &mtk_clk_gate_ops_no_setclr_inv)
0023
0024 static const struct mtk_gate ipu_adl_clks[] = {
0025     GATE_IPU_ADL_I(CLK_IPU_ADL_CABGEN, "ipu_adl_cabgen", "dsp_sel", 24),
0026 };
0027
0028 static int clk_mt8183_ipu_adl_probe(struct platform_device *pdev)
0029 {
0030     struct clk_hw_onecell_data *clk_data;
0031     struct device_node *node = pdev->dev.of_node;
0032
0033     clk_data = mtk_alloc_clk_data(CLK_IPU_ADL_NR_CLK);
0034
0035     mtk_clk_register_gates(node, ipu_adl_clks, ARRAY_SIZE(ipu_adl_clks),
0036             clk_data);
0037
0038     return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0039 }
0040
0041 static const struct of_device_id of_match_clk_mt8183_ipu_adl[] = {
0042     { .compatible = "mediatek,mt8183-ipu_adl", },
0043     {}
0044 };
0045
0046 static struct platform_driver clk_mt8183_ipu_adl_drv = {
0047     .probe = clk_mt8183_ipu_adl_probe,
0048     .driver = {
0049         .name = "clk-mt8183-ipu_adl",
0050         .of_match_table = of_match_clk_mt8183_ipu_adl,
0051     },
0052 };
0053
0054 builtin_platform_driver(clk_mt8183_ipu_adl_drv);