clk/mediatek/clk-mt8183-ipu0.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Copyright (c) 2018 MediaTek Inc.
0004 // Author: Weiyi Lu <weiyi.lu@mediatek.com>
0005
0006 #include <linux/clk-provider.h>
0007 #include <linux/platform_device.h>
0008
0009 #include "clk-mtk.h"
0010 #include "clk-gate.h"
0011
0012 #include <dt-bindings/clock/mt8183-clk.h>
0013
0014 static const struct mtk_gate_regs ipu_core0_cg_regs = {
0015     .set_ofs = 0x4,
0016     .clr_ofs = 0x8,
0017     .sta_ofs = 0x0,
0018 };
0019
0020 #define GATE_IPU_CORE0(_id, _name, _parent, _shift)         \
0021     GATE_MTK(_id, _name, _parent, &ipu_core0_cg_regs, _shift,   \
0022         &mtk_clk_gate_ops_setclr)
0023
0024 static const struct mtk_gate ipu_core0_clks[] = {
0025     GATE_IPU_CORE0(CLK_IPU_CORE0_JTAG, "ipu_core0_jtag", "dsp_sel", 0),
0026     GATE_IPU_CORE0(CLK_IPU_CORE0_AXI, "ipu_core0_axi", "dsp_sel", 1),
0027     GATE_IPU_CORE0(CLK_IPU_CORE0_IPU, "ipu_core0_ipu", "dsp_sel", 2),
0028 };
0029
0030 static int clk_mt8183_ipu_core0_probe(struct platform_device *pdev)
0031 {
0032     struct clk_hw_onecell_data *clk_data;
0033     struct device_node *node = pdev->dev.of_node;
0034
0035     clk_data = mtk_alloc_clk_data(CLK_IPU_CORE0_NR_CLK);
0036
0037     mtk_clk_register_gates(node, ipu_core0_clks, ARRAY_SIZE(ipu_core0_clks),
0038             clk_data);
0039
0040     return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0041 }
0042
0043 static const struct of_device_id of_match_clk_mt8183_ipu_core0[] = {
0044     { .compatible = "mediatek,mt8183-ipu_core0", },
0045     {}
0046 };
0047
0048 static struct platform_driver clk_mt8183_ipu_core0_drv = {
0049     .probe = clk_mt8183_ipu_core0_probe,
0050     .driver = {
0051         .name = "clk-mt8183-ipu_core0",
0052         .of_match_table = of_match_clk_mt8183_ipu_core0,
0053     },
0054 };
0055
0056 builtin_platform_driver(clk_mt8183_ipu_core0_drv);