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0006 #include <linux/clk-provider.h>
0007 #include <linux/platform_device.h>
0008
0009 #include "clk-mtk.h"
0010 #include "clk-gate.h"
0011
0012 #include <dt-bindings/clock/mt8183-clk.h>
0013
0014 static const struct mtk_gate_regs cam_cg_regs = {
0015 .set_ofs = 0x4,
0016 .clr_ofs = 0x8,
0017 .sta_ofs = 0x0,
0018 };
0019
0020 #define GATE_CAM(_id, _name, _parent, _shift) \
0021 GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, \
0022 &mtk_clk_gate_ops_setclr)
0023
0024 static const struct mtk_gate cam_clks[] = {
0025 GATE_CAM(CLK_CAM_LARB6, "cam_larb6", "cam_sel", 0),
0026 GATE_CAM(CLK_CAM_DFP_VAD, "cam_dfp_vad", "cam_sel", 1),
0027 GATE_CAM(CLK_CAM_LARB3, "cam_larb3", "cam_sel", 2),
0028 GATE_CAM(CLK_CAM_CAM, "cam_cam", "cam_sel", 6),
0029 GATE_CAM(CLK_CAM_CAMTG, "cam_camtg", "cam_sel", 7),
0030 GATE_CAM(CLK_CAM_SENINF, "cam_seninf", "cam_sel", 8),
0031 GATE_CAM(CLK_CAM_CAMSV0, "cam_camsv0", "cam_sel", 9),
0032 GATE_CAM(CLK_CAM_CAMSV1, "cam_camsv1", "cam_sel", 10),
0033 GATE_CAM(CLK_CAM_CAMSV2, "cam_camsv2", "cam_sel", 11),
0034 GATE_CAM(CLK_CAM_CCU, "cam_ccu", "cam_sel", 12),
0035 };
0036
0037 static int clk_mt8183_cam_probe(struct platform_device *pdev)
0038 {
0039 struct clk_hw_onecell_data *clk_data;
0040 struct device_node *node = pdev->dev.of_node;
0041
0042 clk_data = mtk_alloc_clk_data(CLK_CAM_NR_CLK);
0043
0044 mtk_clk_register_gates(node, cam_clks, ARRAY_SIZE(cam_clks),
0045 clk_data);
0046
0047 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0048 }
0049
0050 static const struct of_device_id of_match_clk_mt8183_cam[] = {
0051 { .compatible = "mediatek,mt8183-camsys", },
0052 {}
0053 };
0054
0055 static struct platform_driver clk_mt8183_cam_drv = {
0056 .probe = clk_mt8183_cam_probe,
0057 .driver = {
0058 .name = "clk-mt8183-cam",
0059 .of_match_table = of_match_clk_mt8183_cam,
0060 },
0061 };
0062
0063 builtin_platform_driver(clk_mt8183_cam_drv);