clk/mediatek/clk-mt8183-audio.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Copyright (c) 2018 MediaTek Inc.
0004 // Author: Weiyi Lu <weiyi.lu@mediatek.com>
0005
0006 #include <linux/clk-provider.h>
0007 #include <linux/of_platform.h>
0008 #include <linux/platform_device.h>
0009
0010 #include "clk-mtk.h"
0011 #include "clk-gate.h"
0012
0013 #include <dt-bindings/clock/mt8183-clk.h>
0014
0015 static const struct mtk_gate_regs audio0_cg_regs = {
0016     .set_ofs = 0x0,
0017     .clr_ofs = 0x0,
0018     .sta_ofs = 0x0,
0019 };
0020
0021 static const struct mtk_gate_regs audio1_cg_regs = {
0022     .set_ofs = 0x4,
0023     .clr_ofs = 0x4,
0024     .sta_ofs = 0x4,
0025 };
0026
0027 #define GATE_AUDIO0(_id, _name, _parent, _shift)        \
0028     GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift,  \
0029         &mtk_clk_gate_ops_no_setclr)
0030
0031 #define GATE_AUDIO1(_id, _name, _parent, _shift)        \
0032     GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift,  \
0033         &mtk_clk_gate_ops_no_setclr)
0034
0035 static const struct mtk_gate audio_clks[] = {
0036     /* AUDIO0 */
0037     GATE_AUDIO0(CLK_AUDIO_AFE, "aud_afe", "audio_sel",
0038         2),
0039     GATE_AUDIO0(CLK_AUDIO_22M, "aud_22m", "aud_eng1_sel",
0040         8),
0041     GATE_AUDIO0(CLK_AUDIO_24M, "aud_24m", "aud_eng2_sel",
0042         9),
0043     GATE_AUDIO0(CLK_AUDIO_APLL2_TUNER, "aud_apll2_tuner", "aud_eng2_sel",
0044         18),
0045     GATE_AUDIO0(CLK_AUDIO_APLL_TUNER, "aud_apll_tuner", "aud_eng1_sel",
0046         19),
0047     GATE_AUDIO0(CLK_AUDIO_TDM, "aud_tdm", "apll12_divb",
0048         20),
0049     GATE_AUDIO0(CLK_AUDIO_ADC, "aud_adc", "audio_sel",
0050         24),
0051     GATE_AUDIO0(CLK_AUDIO_DAC, "aud_dac", "audio_sel",
0052         25),
0053     GATE_AUDIO0(CLK_AUDIO_DAC_PREDIS, "aud_dac_predis", "audio_sel",
0054         26),
0055     GATE_AUDIO0(CLK_AUDIO_TML, "aud_tml", "audio_sel",
0056         27),
0057     /* AUDIO1 */
0058     GATE_AUDIO1(CLK_AUDIO_I2S1, "aud_i2s1", "audio_sel",
0059         4),
0060     GATE_AUDIO1(CLK_AUDIO_I2S2, "aud_i2s2", "audio_sel",
0061         5),
0062     GATE_AUDIO1(CLK_AUDIO_I2S3, "aud_i2s3", "audio_sel",
0063         6),
0064     GATE_AUDIO1(CLK_AUDIO_I2S4, "aud_i2s4", "audio_sel",
0065         7),
0066     GATE_AUDIO1(CLK_AUDIO_PDN_ADDA6_ADC, "aud_pdn_adda6_adc", "audio_sel",
0067         20),
0068 };
0069
0070 static int clk_mt8183_audio_probe(struct platform_device *pdev)
0071 {
0072     struct clk_hw_onecell_data *clk_data;
0073     int r;
0074     struct device_node *node = pdev->dev.of_node;
0075
0076     clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
0077
0078     mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
0079             clk_data);
0080
0081     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0082     if (r)
0083         return r;
0084
0085     r = devm_of_platform_populate(&pdev->dev);
0086     if (r)
0087         of_clk_del_provider(node);
0088
0089     return r;
0090 }
0091
0092 static const struct of_device_id of_match_clk_mt8183_audio[] = {
0093     { .compatible = "mediatek,mt8183-audiosys", },
0094     {}
0095 };
0096
0097 static struct platform_driver clk_mt8183_audio_drv = {
0098     .probe = clk_mt8183_audio_probe,
0099     .driver = {
0100         .name = "clk-mt8183-audio",
0101         .of_match_table = of_match_clk_mt8183_audio,
0102     },
0103 };
0104
0105 builtin_platform_driver(clk_mt8183_audio_drv);