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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2014 MediaTek Inc.
0004  * Author: James Liao <jamesjj.liao@mediatek.com>
0005  */
0006 
0007 #include <linux/clk.h>
0008 #include <linux/of.h>
0009 #include <linux/of_address.h>
0010 
0011 #include "clk-cpumux.h"
0012 #include "clk-gate.h"
0013 #include "clk-mtk.h"
0014 #include "clk-pll.h"
0015 
0016 #include <dt-bindings/clock/mt8173-clk.h>
0017 
0018 /*
0019  * For some clocks, we don't care what their actual rates are. And these
0020  * clocks may change their rate on different products or different scenarios.
0021  * So we model these clocks' rate as 0, to denote it's not an actual rate.
0022  */
0023 #define DUMMY_RATE      0
0024 
0025 static DEFINE_SPINLOCK(mt8173_clk_lock);
0026 
0027 static const struct mtk_fixed_clk fixed_clks[] __initconst = {
0028     FIXED_CLK(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", "clk26m", DUMMY_RATE),
0029     FIXED_CLK(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk26m", 125 * MHZ),
0030     FIXED_CLK(CLK_TOP_DSI0_DIG, "dsi0_dig", "clk26m", DUMMY_RATE),
0031     FIXED_CLK(CLK_TOP_DSI1_DIG, "dsi1_dig", "clk26m", DUMMY_RATE),
0032     FIXED_CLK(CLK_TOP_LVDS_PXL, "lvds_pxl", "lvdspll", DUMMY_RATE),
0033     FIXED_CLK(CLK_TOP_LVDS_CTS, "lvds_cts", "lvdspll", DUMMY_RATE),
0034 };
0035 
0036 static const struct mtk_fixed_factor top_divs[] __initconst = {
0037     FACTOR(CLK_TOP_ARMCA7PLL_754M, "armca7pll_754m", "armca7pll", 1, 2),
0038     FACTOR(CLK_TOP_ARMCA7PLL_502M, "armca7pll_502m", "armca7pll", 1, 3),
0039 
0040     FACTOR(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2),
0041     FACTOR(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3),
0042     FACTOR(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5),
0043     FACTOR(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7),
0044 
0045     FACTOR(CLK_TOP_TVDPLL_445P5M, "tvdpll_445p5m", "tvdpll", 1, 4),
0046     FACTOR(CLK_TOP_TVDPLL_594M, "tvdpll_594m", "tvdpll", 1, 3),
0047 
0048     FACTOR(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2),
0049     FACTOR(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3),
0050     FACTOR(CLK_TOP_UNIV_249P6M, "univ_249p6m", "univpll", 1, 5),
0051     FACTOR(CLK_TOP_UNIV_178P3M, "univ_178p3m", "univpll", 1, 7),
0052     FACTOR(CLK_TOP_UNIV_48M, "univ_48m", "univpll", 1, 26),
0053 
0054     FACTOR(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", "clk32k", 1, 1),
0055     FACTOR(CLK_TOP_CLKRTC_INT, "clkrtc_int", "clk26m", 1, 793),
0056     FACTOR(CLK_TOP_FPC, "fpc_ck", "clk26m", 1, 1),
0057 
0058     FACTOR(CLK_TOP_HDMITXPLL_D2, "hdmitxpll_d2", "hdmitx_dig_cts", 1, 2),
0059     FACTOR(CLK_TOP_HDMITXPLL_D3, "hdmitxpll_d3", "hdmitx_dig_cts", 1, 3),
0060 
0061     FACTOR(CLK_TOP_ARMCA7PLL_D2, "armca7pll_d2", "armca7pll_754m", 1, 1),
0062     FACTOR(CLK_TOP_ARMCA7PLL_D3, "armca7pll_d3", "armca7pll_502m", 1, 1),
0063 
0064     FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
0065     FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
0066 
0067     FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "clkph_mck_o", 1, 1),
0068     FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "clkph_mck_o", 1, 2),
0069     FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "clkph_mck_o", 1, 4),
0070     FACTOR(CLK_TOP_DMPLL_D8, "dmpll_d8", "clkph_mck_o", 1, 8),
0071     FACTOR(CLK_TOP_DMPLL_D16, "dmpll_d16", "clkph_mck_o", 1, 16),
0072 
0073     FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
0074     FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
0075     FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
0076 
0077     FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
0078     FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
0079 
0080     FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
0081     FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
0082     FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
0083     FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1, 1),
0084     FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2", 1, 2),
0085     FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2", 1, 4),
0086 
0087     FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "main_h546m", 1, 1),
0088     FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "main_h546m", 1, 2),
0089     FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "main_h546m", 1, 4),
0090     FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "main_h546m", 1, 8),
0091     FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "main_h546m", 1, 16),
0092     FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "main_h364m", 1, 1),
0093     FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "main_h364m", 1, 2),
0094     FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "main_h364m", 1, 4),
0095     FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "main_h218p4m", 1, 1),
0096     FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "main_h218p4m", 1, 2),
0097     FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "main_h218p4m", 1, 4),
0098     FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "main_h156m", 1, 1),
0099     FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "main_h156m", 1, 2),
0100     FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "main_h156m", 1, 4),
0101 
0102     FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll_594m", 1, 1),
0103     FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_594m", 1, 2),
0104     FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_594m", 1, 4),
0105     FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_594m", 1, 8),
0106     FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_594m", 1, 16),
0107 
0108     FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univ_624m", 1, 1),
0109     FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univ_624m", 1, 2),
0110     FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univ_624m", 1, 4),
0111     FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univ_624m", 1, 8),
0112     FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univ_416m", 1, 1),
0113     FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univ_416m", 1, 2),
0114     FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univ_416m", 1, 4),
0115     FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univ_416m", 1, 8),
0116     FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univ_249p6m", 1, 1),
0117     FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univ_249p6m", 1, 2),
0118     FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univ_249p6m", 1, 4),
0119     FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univ_249p6m", 1, 8),
0120     FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univ_178p3m", 1, 1),
0121     FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univ_48m", 1, 1),
0122     FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univ_48m", 1, 2),
0123 
0124     FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1, 3),
0125     FACTOR(CLK_TOP_VCODECPLL_370P5, "vcodecpll_370p5", "vcodecpll", 1, 4),
0126 
0127     FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1, 1),
0128     FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll", 1, 2),
0129     FACTOR(CLK_TOP_VENCPLL_D4, "vencpll_d4", "vencpll", 1, 4),
0130 };
0131 
0132 static const char * const axi_parents[] __initconst = {
0133     "clk26m",
0134     "syspll1_d2",
0135     "syspll_d5",
0136     "syspll1_d4",
0137     "univpll_d5",
0138     "univpll2_d2",
0139     "dmpll_d2",
0140     "dmpll_d4"
0141 };
0142 
0143 static const char * const mem_parents[] __initconst = {
0144     "clk26m",
0145     "dmpll_ck"
0146 };
0147 
0148 static const char * const ddrphycfg_parents[] __initconst = {
0149     "clk26m",
0150     "syspll1_d8"
0151 };
0152 
0153 static const char * const mm_parents[] __initconst = {
0154     "clk26m",
0155     "vencpll_d2",
0156     "main_h364m",
0157     "syspll1_d2",
0158     "syspll_d5",
0159     "syspll1_d4",
0160     "univpll1_d2",
0161     "univpll2_d2",
0162     "dmpll_d2"
0163 };
0164 
0165 static const char * const pwm_parents[] __initconst = {
0166     "clk26m",
0167     "univpll2_d4",
0168     "univpll3_d2",
0169     "univpll1_d4"
0170 };
0171 
0172 static const char * const vdec_parents[] __initconst = {
0173     "clk26m",
0174     "vcodecpll_ck",
0175     "tvdpll_445p5m",
0176     "univpll_d3",
0177     "vencpll_d2",
0178     "syspll_d3",
0179     "univpll1_d2",
0180     "mmpll_d2",
0181     "dmpll_d2",
0182     "dmpll_d4"
0183 };
0184 
0185 static const char * const venc_parents[] __initconst = {
0186     "clk26m",
0187     "vcodecpll_ck",
0188     "tvdpll_445p5m",
0189     "univpll_d3",
0190     "vencpll_d2",
0191     "syspll_d3",
0192     "univpll1_d2",
0193     "univpll2_d2",
0194     "dmpll_d2",
0195     "dmpll_d4"
0196 };
0197 
0198 static const char * const mfg_parents[] __initconst = {
0199     "clk26m",
0200     "mmpll_ck",
0201     "dmpll_ck",
0202     "clk26m",
0203     "clk26m",
0204     "clk26m",
0205     "clk26m",
0206     "clk26m",
0207     "clk26m",
0208     "syspll_d3",
0209     "syspll1_d2",
0210     "syspll_d5",
0211     "univpll_d3",
0212     "univpll1_d2",
0213     "univpll_d5",
0214     "univpll2_d2"
0215 };
0216 
0217 static const char * const camtg_parents[] __initconst = {
0218     "clk26m",
0219     "univpll_d26",
0220     "univpll2_d2",
0221     "syspll3_d2",
0222     "syspll3_d4",
0223     "univpll1_d4"
0224 };
0225 
0226 static const char * const uart_parents[] __initconst = {
0227     "clk26m",
0228     "univpll2_d8"
0229 };
0230 
0231 static const char * const spi_parents[] __initconst = {
0232     "clk26m",
0233     "syspll3_d2",
0234     "syspll1_d4",
0235     "syspll4_d2",
0236     "univpll3_d2",
0237     "univpll2_d4",
0238     "univpll1_d8"
0239 };
0240 
0241 static const char * const usb20_parents[] __initconst = {
0242     "clk26m",
0243     "univpll1_d8",
0244     "univpll3_d4"
0245 };
0246 
0247 static const char * const usb30_parents[] __initconst = {
0248     "clk26m",
0249     "univpll3_d2",
0250     "usb_syspll_125m",
0251     "univpll2_d4"
0252 };
0253 
0254 static const char * const msdc50_0_h_parents[] __initconst = {
0255     "clk26m",
0256     "syspll1_d2",
0257     "syspll2_d2",
0258     "syspll4_d2",
0259     "univpll_d5",
0260     "univpll1_d4"
0261 };
0262 
0263 static const char * const msdc50_0_parents[] __initconst = {
0264     "clk26m",
0265     "msdcpll_ck",
0266     "msdcpll_d2",
0267     "univpll1_d4",
0268     "syspll2_d2",
0269     "syspll_d7",
0270     "msdcpll_d4",
0271     "vencpll_d4",
0272     "tvdpll_ck",
0273     "univpll_d2",
0274     "univpll1_d2",
0275     "mmpll_ck",
0276     "msdcpll2_ck",
0277     "msdcpll2_d2",
0278     "msdcpll2_d4"
0279 };
0280 
0281 static const char * const msdc30_1_parents[] __initconst = {
0282     "clk26m",
0283     "univpll2_d2",
0284     "msdcpll_d4",
0285     "univpll1_d4",
0286     "syspll2_d2",
0287     "syspll_d7",
0288     "univpll_d7",
0289     "vencpll_d4"
0290 };
0291 
0292 static const char * const msdc30_2_parents[] __initconst = {
0293     "clk26m",
0294     "univpll2_d2",
0295     "msdcpll_d4",
0296     "univpll1_d4",
0297     "syspll2_d2",
0298     "syspll_d7",
0299     "univpll_d7",
0300     "vencpll_d2"
0301 };
0302 
0303 static const char * const msdc30_3_parents[] __initconst = {
0304     "clk26m",
0305     "msdcpll2_ck",
0306     "msdcpll2_d2",
0307     "univpll2_d2",
0308     "msdcpll2_d4",
0309     "msdcpll_d4",
0310     "univpll1_d4",
0311     "syspll2_d2",
0312     "syspll_d7",
0313     "univpll_d7",
0314     "vencpll_d4",
0315     "msdcpll_ck",
0316     "msdcpll_d2",
0317     "msdcpll_d4"
0318 };
0319 
0320 static const char * const audio_parents[] __initconst = {
0321     "clk26m",
0322     "syspll3_d4",
0323     "syspll4_d4",
0324     "syspll1_d16"
0325 };
0326 
0327 static const char * const aud_intbus_parents[] __initconst = {
0328     "clk26m",
0329     "syspll1_d4",
0330     "syspll4_d2",
0331     "univpll3_d2",
0332     "univpll2_d8",
0333     "dmpll_d4",
0334     "dmpll_d8"
0335 };
0336 
0337 static const char * const pmicspi_parents[] __initconst = {
0338     "clk26m",
0339     "syspll1_d8",
0340     "syspll3_d4",
0341     "syspll1_d16",
0342     "univpll3_d4",
0343     "univpll_d26",
0344     "dmpll_d8",
0345     "dmpll_d16"
0346 };
0347 
0348 static const char * const scp_parents[] __initconst = {
0349     "clk26m",
0350     "syspll1_d2",
0351     "univpll_d5",
0352     "syspll_d5",
0353     "dmpll_d2",
0354     "dmpll_d4"
0355 };
0356 
0357 static const char * const atb_parents[] __initconst = {
0358     "clk26m",
0359     "syspll1_d2",
0360     "univpll_d5",
0361     "dmpll_d2"
0362 };
0363 
0364 static const char * const venc_lt_parents[] __initconst = {
0365     "clk26m",
0366     "univpll_d3",
0367     "vcodecpll_ck",
0368     "tvdpll_445p5m",
0369     "vencpll_d2",
0370     "syspll_d3",
0371     "univpll1_d2",
0372     "univpll2_d2",
0373     "syspll1_d2",
0374     "univpll_d5",
0375     "vcodecpll_370p5",
0376     "dmpll_ck"
0377 };
0378 
0379 static const char * const dpi0_parents[] __initconst = {
0380     "clk26m",
0381     "tvdpll_d2",
0382     "tvdpll_d4",
0383     "clk26m",
0384     "clk26m",
0385     "tvdpll_d8",
0386     "tvdpll_d16"
0387 };
0388 
0389 static const char * const irda_parents[] __initconst = {
0390     "clk26m",
0391     "univpll2_d4",
0392     "syspll2_d4"
0393 };
0394 
0395 static const char * const cci400_parents[] __initconst = {
0396     "clk26m",
0397     "vencpll_ck",
0398     "armca7pll_754m",
0399     "armca7pll_502m",
0400     "univpll_d2",
0401     "syspll_d2",
0402     "msdcpll_ck",
0403     "dmpll_ck"
0404 };
0405 
0406 static const char * const aud_1_parents[] __initconst = {
0407     "clk26m",
0408     "apll1_ck",
0409     "univpll2_d4",
0410     "univpll2_d8"
0411 };
0412 
0413 static const char * const aud_2_parents[] __initconst = {
0414     "clk26m",
0415     "apll2_ck",
0416     "univpll2_d4",
0417     "univpll2_d8"
0418 };
0419 
0420 static const char * const mem_mfg_in_parents[] __initconst = {
0421     "clk26m",
0422     "mmpll_ck",
0423     "dmpll_ck",
0424     "clk26m"
0425 };
0426 
0427 static const char * const axi_mfg_in_parents[] __initconst = {
0428     "clk26m",
0429     "axi_sel",
0430     "dmpll_d2"
0431 };
0432 
0433 static const char * const scam_parents[] __initconst = {
0434     "clk26m",
0435     "syspll3_d2",
0436     "univpll2_d4",
0437     "dmpll_d4"
0438 };
0439 
0440 static const char * const spinfi_ifr_parents[] __initconst = {
0441     "clk26m",
0442     "univpll2_d8",
0443     "univpll3_d4",
0444     "syspll4_d2",
0445     "univpll2_d4",
0446     "univpll3_d2",
0447     "syspll1_d4",
0448     "univpll1_d4"
0449 };
0450 
0451 static const char * const hdmi_parents[] __initconst = {
0452     "clk26m",
0453     "hdmitx_dig_cts",
0454     "hdmitxpll_d2",
0455     "hdmitxpll_d3"
0456 };
0457 
0458 static const char * const dpilvds_parents[] __initconst = {
0459     "clk26m",
0460     "lvdspll",
0461     "lvdspll_d2",
0462     "lvdspll_d4",
0463     "lvdspll_d8",
0464     "fpc_ck"
0465 };
0466 
0467 static const char * const msdc50_2_h_parents[] __initconst = {
0468     "clk26m",
0469     "syspll1_d2",
0470     "syspll2_d2",
0471     "syspll4_d2",
0472     "univpll_d5",
0473     "univpll1_d4"
0474 };
0475 
0476 static const char * const hdcp_parents[] __initconst = {
0477     "clk26m",
0478     "syspll4_d2",
0479     "syspll3_d4",
0480     "univpll2_d4"
0481 };
0482 
0483 static const char * const hdcp_24m_parents[] __initconst = {
0484     "clk26m",
0485     "univpll_d26",
0486     "univpll_d52",
0487     "univpll2_d8"
0488 };
0489 
0490 static const char * const rtc_parents[] __initconst = {
0491     "clkrtc_int",
0492     "clkrtc_ext",
0493     "clk26m",
0494     "univpll3_d8"
0495 };
0496 
0497 static const char * const i2s0_m_ck_parents[] __initconst = {
0498     "apll1_div1",
0499     "apll2_div1"
0500 };
0501 
0502 static const char * const i2s1_m_ck_parents[] __initconst = {
0503     "apll1_div2",
0504     "apll2_div2"
0505 };
0506 
0507 static const char * const i2s2_m_ck_parents[] __initconst = {
0508     "apll1_div3",
0509     "apll2_div3"
0510 };
0511 
0512 static const char * const i2s3_m_ck_parents[] __initconst = {
0513     "apll1_div4",
0514     "apll2_div4"
0515 };
0516 
0517 static const char * const i2s3_b_ck_parents[] __initconst = {
0518     "apll1_div5",
0519     "apll2_div5"
0520 };
0521 
0522 static const char * const ca53_parents[] __initconst = {
0523     "clk26m",
0524     "armca7pll",
0525     "mainpll",
0526     "univpll"
0527 };
0528 
0529 static const char * const ca72_parents[] __initconst = {
0530     "clk26m",
0531     "armca15pll",
0532     "mainpll",
0533     "univpll"
0534 };
0535 
0536 static const struct mtk_composite cpu_muxes[] __initconst = {
0537     MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2),
0538     MUX(CLK_INFRA_CA72SEL, "infra_ca72_sel", ca72_parents, 0x0000, 2, 2),
0539 };
0540 
0541 static const struct mtk_composite top_muxes[] __initconst = {
0542     /* CLK_CFG_0 */
0543     MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3),
0544     MUX(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 1),
0545     MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 0x0040, 16, 1, 23),
0546     MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x0040, 24, 4, 31),
0547     /* CLK_CFG_1 */
0548     MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7),
0549     MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x0050, 8, 4, 15),
0550     MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0050, 16, 4, 23),
0551     MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0050, 24, 4, 31),
0552     /* CLK_CFG_2 */
0553     MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0060, 0, 3, 7),
0554     MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
0555     MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0060, 16, 3, 23),
0556     MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x0060, 24, 2, 31),
0557     /* CLK_CFG_3 */
0558     MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel", usb30_parents, 0x0070, 0, 2, 7),
0559     MUX_GATE(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", msdc50_0_h_parents, 0x0070, 8, 3, 15),
0560     MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents, 0x0070, 16, 4, 23),
0561     MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents, 0x0070, 24, 3, 31),
0562     /* CLK_CFG_4 */
0563     MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_2_parents, 0x0080, 0, 3, 7),
0564     MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents, 0x0080, 8, 4, 15),
0565     MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x0080, 16, 2, 23),
0566     MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 0x0080, 24, 3, 31),
0567     /* CLK_CFG_5 */
0568     MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x0090, 0, 3, 7 /* 7:5 */),
0569     MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x0090, 8, 3, 15),
0570     MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x0090, 16, 2, 23),
0571     MUX_GATE(CLK_TOP_VENC_LT_SEL, "venclt_sel", venc_lt_parents, 0x0090, 24, 4, 31),
0572     /* CLK_CFG_6 */
0573     /*
0574      * The dpi0_sel clock should not propagate rate changes to its parent
0575      * clock so the dpi driver can have full control over PLL and divider.
0576      */
0577     MUX_GATE_FLAGS(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0, 3, 7, 0),
0578     MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x00a0, 8, 2, 15),
0579     MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents, 0x00a0, 16, 3, 23),
0580     MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2, 31),
0581     /* CLK_CFG_7 */
0582     MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0x00b0, 0, 2, 7),
0583     MUX_GATE(CLK_TOP_MEM_MFG_IN_SEL, "mem_mfg_in_sel", mem_mfg_in_parents, 0x00b0, 8, 2, 15),
0584     MUX_GATE(CLK_TOP_AXI_MFG_IN_SEL, "axi_mfg_in_sel", axi_mfg_in_parents, 0x00b0, 16, 2, 23),
0585     MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel", scam_parents, 0x00b0, 24, 2, 31),
0586     /* CLK_CFG_12 */
0587     MUX_GATE(CLK_TOP_SPINFI_IFR_SEL, "spinfi_ifr_sel", spinfi_ifr_parents, 0x00c0, 0, 3, 7),
0588     MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents, 0x00c0, 8, 2, 15),
0589     MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x00c0, 24, 3, 31),
0590     /* CLK_CFG_13 */
0591     MUX_GATE(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents, 0x00d0, 0, 3, 7),
0592     MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", hdcp_parents, 0x00d0, 8, 2, 15),
0593     MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel", hdcp_24m_parents, 0x00d0, 16, 2, 23),
0594     MUX(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x00d0, 24, 2),
0595 
0596     DIV_GATE(CLK_TOP_APLL1_DIV0, "apll1_div0", "aud_1_sel", 0x12c, 8, 0x120, 4, 24),
0597     DIV_GATE(CLK_TOP_APLL1_DIV1, "apll1_div1", "aud_1_sel", 0x12c, 9, 0x124, 8, 0),
0598     DIV_GATE(CLK_TOP_APLL1_DIV2, "apll1_div2", "aud_1_sel", 0x12c, 10, 0x124, 8, 8),
0599     DIV_GATE(CLK_TOP_APLL1_DIV3, "apll1_div3", "aud_1_sel", 0x12c, 11, 0x124, 8, 16),
0600     DIV_GATE(CLK_TOP_APLL1_DIV4, "apll1_div4", "aud_1_sel", 0x12c, 12, 0x124, 8, 24),
0601     DIV_GATE(CLK_TOP_APLL1_DIV5, "apll1_div5", "apll1_div4", 0x12c, 13, 0x12c, 4, 0),
0602 
0603     DIV_GATE(CLK_TOP_APLL2_DIV0, "apll2_div0", "aud_2_sel", 0x12c, 16, 0x120, 4, 28),
0604     DIV_GATE(CLK_TOP_APLL2_DIV1, "apll2_div1", "aud_2_sel", 0x12c, 17, 0x128, 8, 0),
0605     DIV_GATE(CLK_TOP_APLL2_DIV2, "apll2_div2", "aud_2_sel", 0x12c, 18, 0x128, 8, 8),
0606     DIV_GATE(CLK_TOP_APLL2_DIV3, "apll2_div3", "aud_2_sel", 0x12c, 19, 0x128, 8, 16),
0607     DIV_GATE(CLK_TOP_APLL2_DIV4, "apll2_div4", "aud_2_sel", 0x12c, 20, 0x128, 8, 24),
0608     DIV_GATE(CLK_TOP_APLL2_DIV5, "apll2_div5", "apll2_div4", 0x12c, 21, 0x12c, 4, 4),
0609 
0610     MUX(CLK_TOP_I2S0_M_SEL, "i2s0_m_ck_sel", i2s0_m_ck_parents, 0x120, 4, 1),
0611     MUX(CLK_TOP_I2S1_M_SEL, "i2s1_m_ck_sel", i2s1_m_ck_parents, 0x120, 5, 1),
0612     MUX(CLK_TOP_I2S2_M_SEL, "i2s2_m_ck_sel", i2s2_m_ck_parents, 0x120, 6, 1),
0613     MUX(CLK_TOP_I2S3_M_SEL, "i2s3_m_ck_sel", i2s3_m_ck_parents, 0x120, 7, 1),
0614     MUX(CLK_TOP_I2S3_B_SEL, "i2s3_b_ck_sel", i2s3_b_ck_parents, 0x120, 8, 1),
0615 };
0616 
0617 static const struct mtk_gate_regs infra_cg_regs __initconst = {
0618     .set_ofs = 0x0040,
0619     .clr_ofs = 0x0044,
0620     .sta_ofs = 0x0048,
0621 };
0622 
0623 #define GATE_ICG(_id, _name, _parent, _shift) { \
0624         .id = _id,                  \
0625         .name = _name,                  \
0626         .parent_name = _parent,             \
0627         .regs = &infra_cg_regs,             \
0628         .shift = _shift,                \
0629         .ops = &mtk_clk_gate_ops_setclr,        \
0630     }
0631 
0632 static const struct mtk_gate infra_clks[] __initconst = {
0633     GATE_ICG(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0),
0634     GATE_ICG(CLK_INFRA_SMI, "infra_smi", "mm_sel", 1),
0635     GATE_ICG(CLK_INFRA_AUDIO, "infra_audio", "aud_intbus_sel", 5),
0636     GATE_ICG(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6),
0637     GATE_ICG(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "axi_sel", 7),
0638     GATE_ICG(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8),
0639     GATE_ICG(CLK_INFRA_CPUM, "infra_cpum", "cpum_ck", 15),
0640     GATE_ICG(CLK_INFRA_KP, "infra_kp", "axi_sel", 16),
0641     GATE_ICG(CLK_INFRA_CEC, "infra_cec", "clk26m", 18),
0642     GATE_ICG(CLK_INFRA_PMICSPI, "infra_pmicspi", "pmicspi_sel", 22),
0643     GATE_ICG(CLK_INFRA_PMICWRAP, "infra_pmicwrap", "axi_sel", 23),
0644 };
0645 
0646 static const struct mtk_fixed_factor infra_divs[] __initconst = {
0647     FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
0648 };
0649 
0650 static const struct mtk_gate_regs peri0_cg_regs __initconst = {
0651     .set_ofs = 0x0008,
0652     .clr_ofs = 0x0010,
0653     .sta_ofs = 0x0018,
0654 };
0655 
0656 static const struct mtk_gate_regs peri1_cg_regs __initconst = {
0657     .set_ofs = 0x000c,
0658     .clr_ofs = 0x0014,
0659     .sta_ofs = 0x001c,
0660 };
0661 
0662 #define GATE_PERI0(_id, _name, _parent, _shift) {   \
0663         .id = _id,                  \
0664         .name = _name,                  \
0665         .parent_name = _parent,             \
0666         .regs = &peri0_cg_regs,             \
0667         .shift = _shift,                \
0668         .ops = &mtk_clk_gate_ops_setclr,        \
0669     }
0670 
0671 #define GATE_PERI1(_id, _name, _parent, _shift) {   \
0672         .id = _id,                  \
0673         .name = _name,                  \
0674         .parent_name = _parent,             \
0675         .regs = &peri1_cg_regs,             \
0676         .shift = _shift,                \
0677         .ops = &mtk_clk_gate_ops_setclr,        \
0678     }
0679 
0680 static const struct mtk_gate peri_gates[] __initconst = {
0681     /* PERI0 */
0682     GATE_PERI0(CLK_PERI_NFI, "peri_nfi", "axi_sel", 0),
0683     GATE_PERI0(CLK_PERI_THERM, "peri_therm", "axi_sel", 1),
0684     GATE_PERI0(CLK_PERI_PWM1, "peri_pwm1", "axi_sel", 2),
0685     GATE_PERI0(CLK_PERI_PWM2, "peri_pwm2", "axi_sel", 3),
0686     GATE_PERI0(CLK_PERI_PWM3, "peri_pwm3", "axi_sel", 4),
0687     GATE_PERI0(CLK_PERI_PWM4, "peri_pwm4", "axi_sel", 5),
0688     GATE_PERI0(CLK_PERI_PWM5, "peri_pwm5", "axi_sel", 6),
0689     GATE_PERI0(CLK_PERI_PWM6, "peri_pwm6", "axi_sel", 7),
0690     GATE_PERI0(CLK_PERI_PWM7, "peri_pwm7", "axi_sel", 8),
0691     GATE_PERI0(CLK_PERI_PWM, "peri_pwm", "axi_sel", 9),
0692     GATE_PERI0(CLK_PERI_USB0, "peri_usb0", "usb20_sel", 10),
0693     GATE_PERI0(CLK_PERI_USB1, "peri_usb1", "usb20_sel", 11),
0694     GATE_PERI0(CLK_PERI_AP_DMA, "peri_ap_dma", "axi_sel", 12),
0695     GATE_PERI0(CLK_PERI_MSDC30_0, "peri_msdc30_0", "msdc50_0_sel", 13),
0696     GATE_PERI0(CLK_PERI_MSDC30_1, "peri_msdc30_1", "msdc30_1_sel", 14),
0697     GATE_PERI0(CLK_PERI_MSDC30_2, "peri_msdc30_2", "msdc30_2_sel", 15),
0698     GATE_PERI0(CLK_PERI_MSDC30_3, "peri_msdc30_3", "msdc30_3_sel", 16),
0699     GATE_PERI0(CLK_PERI_NLI_ARB, "peri_nli_arb", "axi_sel", 17),
0700     GATE_PERI0(CLK_PERI_IRDA, "peri_irda", "irda_sel", 18),
0701     GATE_PERI0(CLK_PERI_UART0, "peri_uart0", "axi_sel", 19),
0702     GATE_PERI0(CLK_PERI_UART1, "peri_uart1", "axi_sel", 20),
0703     GATE_PERI0(CLK_PERI_UART2, "peri_uart2", "axi_sel", 21),
0704     GATE_PERI0(CLK_PERI_UART3, "peri_uart3", "axi_sel", 22),
0705     GATE_PERI0(CLK_PERI_I2C0, "peri_i2c0", "axi_sel", 23),
0706     GATE_PERI0(CLK_PERI_I2C1, "peri_i2c1", "axi_sel", 24),
0707     GATE_PERI0(CLK_PERI_I2C2, "peri_i2c2", "axi_sel", 25),
0708     GATE_PERI0(CLK_PERI_I2C3, "peri_i2c3", "axi_sel", 26),
0709     GATE_PERI0(CLK_PERI_I2C4, "peri_i2c4", "axi_sel", 27),
0710     GATE_PERI0(CLK_PERI_AUXADC, "peri_auxadc", "clk26m", 28),
0711     GATE_PERI0(CLK_PERI_SPI0, "peri_spi0", "spi_sel", 29),
0712     GATE_PERI0(CLK_PERI_I2C5, "peri_i2c5", "axi_sel", 30),
0713     GATE_PERI0(CLK_PERI_NFIECC, "peri_nfiecc", "axi_sel", 31),
0714     /* PERI1 */
0715     GATE_PERI1(CLK_PERI_SPI, "peri_spi", "spi_sel", 0),
0716     GATE_PERI1(CLK_PERI_IRRX, "peri_irrx", "spi_sel", 1),
0717     GATE_PERI1(CLK_PERI_I2C6, "peri_i2c6", "axi_sel", 2),
0718 };
0719 
0720 static const char * const uart_ck_sel_parents[] __initconst = {
0721     "clk26m",
0722     "uart_sel",
0723 };
0724 
0725 static const struct mtk_composite peri_clks[] __initconst = {
0726     MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1),
0727     MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1),
0728     MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1),
0729     MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
0730 };
0731 
0732 static const struct mtk_gate_regs cg_regs_4_8_0 __initconst = {
0733     .set_ofs = 0x0004,
0734     .clr_ofs = 0x0008,
0735     .sta_ofs = 0x0000,
0736 };
0737 
0738 #define GATE_IMG(_id, _name, _parent, _shift) {         \
0739         .id = _id,                  \
0740         .name = _name,                  \
0741         .parent_name = _parent,             \
0742         .regs = &cg_regs_4_8_0,             \
0743         .shift = _shift,                \
0744         .ops = &mtk_clk_gate_ops_setclr,        \
0745     }
0746 
0747 static const struct mtk_gate img_clks[] __initconst = {
0748     GATE_IMG(CLK_IMG_LARB2_SMI, "img_larb2_smi", "mm_sel", 0),
0749     GATE_IMG(CLK_IMG_CAM_SMI, "img_cam_smi", "mm_sel", 5),
0750     GATE_IMG(CLK_IMG_CAM_CAM, "img_cam_cam", "mm_sel", 6),
0751     GATE_IMG(CLK_IMG_SEN_TG, "img_sen_tg", "camtg_sel", 7),
0752     GATE_IMG(CLK_IMG_SEN_CAM, "img_sen_cam", "mm_sel", 8),
0753     GATE_IMG(CLK_IMG_CAM_SV, "img_cam_sv", "mm_sel", 9),
0754     GATE_IMG(CLK_IMG_FD, "img_fd", "mm_sel", 11),
0755 };
0756 
0757 static const struct mtk_gate_regs vdec0_cg_regs __initconst = {
0758     .set_ofs = 0x0000,
0759     .clr_ofs = 0x0004,
0760     .sta_ofs = 0x0000,
0761 };
0762 
0763 static const struct mtk_gate_regs vdec1_cg_regs __initconst = {
0764     .set_ofs = 0x0008,
0765     .clr_ofs = 0x000c,
0766     .sta_ofs = 0x0008,
0767 };
0768 
0769 #define GATE_VDEC0(_id, _name, _parent, _shift) {       \
0770         .id = _id,                  \
0771         .name = _name,                  \
0772         .parent_name = _parent,             \
0773         .regs = &vdec0_cg_regs,             \
0774         .shift = _shift,                \
0775         .ops = &mtk_clk_gate_ops_setclr_inv,        \
0776     }
0777 
0778 #define GATE_VDEC1(_id, _name, _parent, _shift) {       \
0779         .id = _id,                  \
0780         .name = _name,                  \
0781         .parent_name = _parent,             \
0782         .regs = &vdec1_cg_regs,             \
0783         .shift = _shift,                \
0784         .ops = &mtk_clk_gate_ops_setclr_inv,        \
0785     }
0786 
0787 static const struct mtk_gate vdec_clks[] __initconst = {
0788     GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0),
0789     GATE_VDEC1(CLK_VDEC_LARB_CKEN, "vdec_larb_cken", "mm_sel", 0),
0790 };
0791 
0792 #define GATE_VENC(_id, _name, _parent, _shift) {        \
0793         .id = _id,                  \
0794         .name = _name,                  \
0795         .parent_name = _parent,             \
0796         .regs = &cg_regs_4_8_0,             \
0797         .shift = _shift,                \
0798         .ops = &mtk_clk_gate_ops_setclr_inv,        \
0799     }
0800 
0801 static const struct mtk_gate venc_clks[] __initconst = {
0802     GATE_VENC(CLK_VENC_CKE0, "venc_cke0", "mm_sel", 0),
0803     GATE_VENC(CLK_VENC_CKE1, "venc_cke1", "venc_sel", 4),
0804     GATE_VENC(CLK_VENC_CKE2, "venc_cke2", "venc_sel", 8),
0805     GATE_VENC(CLK_VENC_CKE3, "venc_cke3", "venc_sel", 12),
0806 };
0807 
0808 #define GATE_VENCLT(_id, _name, _parent, _shift) {      \
0809         .id = _id,                  \
0810         .name = _name,                  \
0811         .parent_name = _parent,             \
0812         .regs = &cg_regs_4_8_0,             \
0813         .shift = _shift,                \
0814         .ops = &mtk_clk_gate_ops_setclr_inv,        \
0815     }
0816 
0817 static const struct mtk_gate venclt_clks[] __initconst = {
0818     GATE_VENCLT(CLK_VENCLT_CKE0, "venclt_cke0", "mm_sel", 0),
0819     GATE_VENCLT(CLK_VENCLT_CKE1, "venclt_cke1", "venclt_sel", 4),
0820 };
0821 
0822 static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
0823 static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
0824 
0825 static const struct mtk_clk_rst_desc clk_rst_desc[] = {
0826     /* infrasys */
0827     {
0828         .version = MTK_RST_SIMPLE,
0829         .rst_bank_ofs = infrasys_rst_ofs,
0830         .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
0831     },
0832     /* pericfg */
0833     {
0834         .version = MTK_RST_SIMPLE,
0835         .rst_bank_ofs = pericfg_rst_ofs,
0836         .rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
0837     }
0838 };
0839 
0840 static struct clk_hw_onecell_data *mt8173_top_clk_data __initdata;
0841 static struct clk_hw_onecell_data *mt8173_pll_clk_data __initdata;
0842 
0843 static void __init mtk_clk_enable_critical(void)
0844 {
0845     if (!mt8173_top_clk_data || !mt8173_pll_clk_data)
0846         return;
0847 
0848     clk_prepare_enable(mt8173_pll_clk_data->hws[CLK_APMIXED_ARMCA15PLL]->clk);
0849     clk_prepare_enable(mt8173_pll_clk_data->hws[CLK_APMIXED_ARMCA7PLL]->clk);
0850     clk_prepare_enable(mt8173_top_clk_data->hws[CLK_TOP_MEM_SEL]->clk);
0851     clk_prepare_enable(mt8173_top_clk_data->hws[CLK_TOP_DDRPHYCFG_SEL]->clk);
0852     clk_prepare_enable(mt8173_top_clk_data->hws[CLK_TOP_CCI400_SEL]->clk);
0853     clk_prepare_enable(mt8173_top_clk_data->hws[CLK_TOP_RTC_SEL]->clk);
0854 }
0855 
0856 static void __init mtk_topckgen_init(struct device_node *node)
0857 {
0858     struct clk_hw_onecell_data *clk_data;
0859     void __iomem *base;
0860     int r;
0861 
0862     base = of_iomap(node, 0);
0863     if (!base) {
0864         pr_err("%s(): ioremap failed\n", __func__);
0865         return;
0866     }
0867 
0868     mt8173_top_clk_data = clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
0869 
0870     mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), clk_data);
0871     mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
0872     mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
0873             &mt8173_clk_lock, clk_data);
0874 
0875     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0876     if (r)
0877         pr_err("%s(): could not register clock provider: %d\n",
0878             __func__, r);
0879 
0880     mtk_clk_enable_critical();
0881 }
0882 CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8173-topckgen", mtk_topckgen_init);
0883 
0884 static void __init mtk_infrasys_init(struct device_node *node)
0885 {
0886     struct clk_hw_onecell_data *clk_data;
0887     int r;
0888 
0889     clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
0890 
0891     mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
0892                         clk_data);
0893     mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
0894 
0895     mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
0896                   clk_data);
0897 
0898     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0899     if (r)
0900         pr_err("%s(): could not register clock provider: %d\n",
0901             __func__, r);
0902 
0903     mtk_register_reset_controller(node, &clk_rst_desc[0]);
0904 }
0905 CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init);
0906 
0907 static void __init mtk_pericfg_init(struct device_node *node)
0908 {
0909     struct clk_hw_onecell_data *clk_data;
0910     int r;
0911     void __iomem *base;
0912 
0913     base = of_iomap(node, 0);
0914     if (!base) {
0915         pr_err("%s(): ioremap failed\n", __func__);
0916         return;
0917     }
0918 
0919     clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
0920 
0921     mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates),
0922                         clk_data);
0923     mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base,
0924             &mt8173_clk_lock, clk_data);
0925 
0926     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0927     if (r)
0928         pr_err("%s(): could not register clock provider: %d\n",
0929             __func__, r);
0930 
0931     mtk_register_reset_controller(node, &clk_rst_desc[1]);
0932 }
0933 CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init);
0934 
0935 struct mtk_clk_usb {
0936     int id;
0937     const char *name;
0938     const char *parent;
0939     u32 reg_ofs;
0940 };
0941 
0942 #define APMIXED_USB(_id, _name, _parent, _reg_ofs) {            \
0943         .id = _id,                      \
0944         .name = _name,                      \
0945         .parent = _parent,                  \
0946         .reg_ofs = _reg_ofs,                    \
0947     }
0948 
0949 static const struct mtk_clk_usb apmixed_usb[] __initconst = {
0950     APMIXED_USB(CLK_APMIXED_REF2USB_TX, "ref2usb_tx", "clk26m", 0x8),
0951 };
0952 
0953 #define MT8173_PLL_FMAX     (3000UL * MHZ)
0954 
0955 #define CON0_MT8173_RST_BAR BIT(24)
0956 
0957 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,   \
0958             _pd_reg, _pd_shift, _tuner_reg, _pcw_reg,   \
0959             _pcw_shift, _div_table) {           \
0960         .id = _id,                      \
0961         .name = _name,                      \
0962         .reg = _reg,                        \
0963         .pwr_reg = _pwr_reg,                    \
0964         .en_mask = _en_mask,                    \
0965         .flags = _flags,                    \
0966         .rst_bar_mask = CON0_MT8173_RST_BAR,            \
0967         .fmax = MT8173_PLL_FMAX,                \
0968         .pcwbits = _pcwbits,                    \
0969         .pd_reg = _pd_reg,                  \
0970         .pd_shift = _pd_shift,                  \
0971         .tuner_reg = _tuner_reg,                \
0972         .pcw_reg = _pcw_reg,                    \
0973         .pcw_shift = _pcw_shift,                \
0974         .div_table = _div_table,                \
0975     }
0976 
0977 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
0978             _pd_reg, _pd_shift, _tuner_reg, _pcw_reg,   \
0979             _pcw_shift)                 \
0980         PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
0981             _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
0982             NULL)
0983 
0984 static const struct mtk_pll_div_table mmpll_div_table[] = {
0985     { .div = 0, .freq = MT8173_PLL_FMAX },
0986     { .div = 1, .freq = 1000000000 },
0987     { .div = 2, .freq = 702000000 },
0988     { .div = 3, .freq = 253500000 },
0989     { .div = 4, .freq = 126750000 },
0990     { } /* sentinel */
0991 };
0992 
0993 static const struct mtk_pll_data plls[] = {
0994     PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0, 0, 21, 0x204, 24, 0x0, 0x204, 0),
0995     PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0, 0, 21, 0x214, 24, 0x0, 0x214, 0),
0996     PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000100, HAVE_RST_BAR, 21, 0x220, 4, 0x0, 0x224, 0),
0997     PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000000, HAVE_RST_BAR, 7, 0x230, 4, 0x0, 0x234, 14),
0998     PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0, 0, 21, 0x244, 24, 0x0, 0x244, 0, mmpll_div_table),
0999     PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0, 0, 21, 0x250, 4, 0x0, 0x254, 0),
1000     PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0, 0, 21, 0x260, 4, 0x0, 0x264, 0),
1001     PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0, 0, 21, 0x270, 4, 0x0, 0x274, 0),
1002     PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0, 0, 21, 0x280, 4, 0x0, 0x284, 0),
1003     PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0, 0, 21, 0x290, 4, 0x0, 0x294, 0),
1004     PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0, 0, 31, 0x2a0, 4, 0x2a4, 0x2a4, 0),
1005     PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0, 0, 31, 0x2b4, 4, 0x2b8, 0x2b8, 0),
1006     PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2d0, 0x2dc, 0, 0, 21, 0x2d0, 4, 0x0, 0x2d4, 0),
1007     PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x2f0, 0x2fc, 0, 0, 21, 0x2f0, 4, 0x0, 0x2f4, 0),
1008 };
1009 
1010 static void __init mtk_apmixedsys_init(struct device_node *node)
1011 {
1012     struct clk_hw_onecell_data *clk_data;
1013     void __iomem *base;
1014     struct clk_hw *hw;
1015     int r, i;
1016 
1017     base = of_iomap(node, 0);
1018     if (!base) {
1019         pr_err("%s(): ioremap failed\n", __func__);
1020         return;
1021     }
1022 
1023     mt8173_pll_clk_data = clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
1024     if (!clk_data) {
1025         iounmap(base);
1026         return;
1027     }
1028 
1029     mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
1030 
1031     for (i = 0; i < ARRAY_SIZE(apmixed_usb); i++) {
1032         const struct mtk_clk_usb *cku = &apmixed_usb[i];
1033 
1034         hw = mtk_clk_register_ref2usb_tx(cku->name, cku->parent, base + cku->reg_ofs);
1035         if (IS_ERR(hw)) {
1036             pr_err("Failed to register clk %s: %ld\n", cku->name, PTR_ERR(hw));
1037             continue;
1038         }
1039 
1040         clk_data->hws[cku->id] = hw;
1041     }
1042 
1043     hw = clk_hw_register_divider(NULL, "hdmi_ref", "tvdpll_594m", 0,
1044                      base + 0x40, 16, 3, CLK_DIVIDER_POWER_OF_TWO,
1045                      NULL);
1046     clk_data->hws[CLK_APMIXED_HDMI_REF] = hw;
1047 
1048     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1049     if (r)
1050         pr_err("%s(): could not register clock provider: %d\n",
1051             __func__, r);
1052 
1053     mtk_clk_enable_critical();
1054 }
1055 CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8173-apmixedsys",
1056         mtk_apmixedsys_init);
1057 
1058 static void __init mtk_imgsys_init(struct device_node *node)
1059 {
1060     struct clk_hw_onecell_data *clk_data;
1061     int r;
1062 
1063     clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
1064 
1065     mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
1066                         clk_data);
1067 
1068     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1069 
1070     if (r)
1071         pr_err("%s(): could not register clock provider: %d\n",
1072             __func__, r);
1073 }
1074 CLK_OF_DECLARE(mtk_imgsys, "mediatek,mt8173-imgsys", mtk_imgsys_init);
1075 
1076 static void __init mtk_vdecsys_init(struct device_node *node)
1077 {
1078     struct clk_hw_onecell_data *clk_data;
1079     int r;
1080 
1081     clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
1082 
1083     mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
1084                         clk_data);
1085 
1086     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1087     if (r)
1088         pr_err("%s(): could not register clock provider: %d\n",
1089             __func__, r);
1090 }
1091 CLK_OF_DECLARE(mtk_vdecsys, "mediatek,mt8173-vdecsys", mtk_vdecsys_init);
1092 
1093 static void __init mtk_vencsys_init(struct device_node *node)
1094 {
1095     struct clk_hw_onecell_data *clk_data;
1096     int r;
1097 
1098     clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK);
1099 
1100     mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
1101                         clk_data);
1102 
1103     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1104     if (r)
1105         pr_err("%s(): could not register clock provider: %d\n",
1106             __func__, r);
1107 }
1108 CLK_OF_DECLARE(mtk_vencsys, "mediatek,mt8173-vencsys", mtk_vencsys_init);
1109 
1110 static void __init mtk_vencltsys_init(struct device_node *node)
1111 {
1112     struct clk_hw_onecell_data *clk_data;
1113     int r;
1114 
1115     clk_data = mtk_alloc_clk_data(CLK_VENCLT_NR_CLK);
1116 
1117     mtk_clk_register_gates(node, venclt_clks, ARRAY_SIZE(venclt_clks),
1118                         clk_data);
1119 
1120     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1121     if (r)
1122         pr_err("%s(): could not register clock provider: %d\n",
1123             __func__, r);
1124 }
1125 CLK_OF_DECLARE(mtk_vencltsys, "mediatek,mt8173-vencltsys", mtk_vencltsys_init);
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