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0009 #include <linux/delay.h>
0010 #include <linux/of.h>
0011 #include <linux/of_address.h>
0012 #include <linux/slab.h>
0013 #include <linux/mfd/syscon.h>
0014
0015 #include "clk-gate.h"
0016 #include "clk-mtk.h"
0017 #include "clk-pll.h"
0018
0019 #include <dt-bindings/clock/mt8167-clk.h>
0020
0021 static DEFINE_SPINLOCK(mt8167_clk_lock);
0022
0023 static const struct mtk_fixed_clk fixed_clks[] __initconst = {
0024 FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0),
0025 FIXED_CLK(CLK_TOP_I2S_INFRA_BCK, "i2s_infra_bck", "clk_null", 26000000),
0026 FIXED_CLK(CLK_TOP_MEMPLL, "mempll", "clk26m", 800000000),
0027 FIXED_CLK(CLK_TOP_DSI0_LNTC_DSICK, "dsi0_lntc_dsick", "clk26m", 75000000),
0028 FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", "clk26m", 75000000),
0029 FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx_dig_cts", "clk26m", 52500000),
0030 };
0031
0032 static const struct mtk_fixed_factor top_divs[] __initconst = {
0033 FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
0034 FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2),
0035 FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4),
0036 FACTOR(CLK_TOP_MAINPLL_D8, "mainpll_d8", "mainpll", 1, 8),
0037 FACTOR(CLK_TOP_MAINPLL_D16, "mainpll_d16", "mainpll", 1, 16),
0038 FACTOR(CLK_TOP_MAINPLL_D11, "mainpll_d11", "mainpll", 1, 11),
0039 FACTOR(CLK_TOP_MAINPLL_D22, "mainpll_d22", "mainpll", 1, 22),
0040 FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
0041 FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6),
0042 FACTOR(CLK_TOP_MAINPLL_D12, "mainpll_d12", "mainpll", 1, 12),
0043 FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
0044 FACTOR(CLK_TOP_MAINPLL_D10, "mainpll_d10", "mainpll", 1, 10),
0045 FACTOR(CLK_TOP_MAINPLL_D20, "mainpll_d20", "mainpll", 1, 20),
0046 FACTOR(CLK_TOP_MAINPLL_D40, "mainpll_d40", "mainpll", 1, 40),
0047 FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
0048 FACTOR(CLK_TOP_MAINPLL_D14, "mainpll_d14", "mainpll", 1, 14),
0049 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
0050 FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
0051 FACTOR(CLK_TOP_UNIVPLL_D8, "univpll_d8", "univpll", 1, 8),
0052 FACTOR(CLK_TOP_UNIVPLL_D16, "univpll_d16", "univpll", 1, 16),
0053 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
0054 FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6),
0055 FACTOR(CLK_TOP_UNIVPLL_D12, "univpll_d12", "univpll", 1, 12),
0056 FACTOR(CLK_TOP_UNIVPLL_D24, "univpll_d24", "univpll", 1, 24),
0057 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
0058 FACTOR(CLK_TOP_UNIVPLL_D20, "univpll_d20", "univpll", 1, 20),
0059 FACTOR(CLK_TOP_MMPLL380M, "mmpll380m", "mmpll", 1, 1),
0060 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
0061 FACTOR(CLK_TOP_MMPLL_200M, "mmpll_200m", "mmpll", 1, 3),
0062 FACTOR(CLK_TOP_LVDSPLL, "lvdspll_ck", "lvdspll", 1, 1),
0063 FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
0064 FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
0065 FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
0066 FACTOR(CLK_TOP_USB_PHY48M, "usb_phy48m_ck", "univpll", 1, 26),
0067 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
0068 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2),
0069 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "rg_apll1_d2_en", 1, 2),
0070 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "rg_apll1_d4_en", 1, 2),
0071 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
0072 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, 2),
0073 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "rg_apll2_d2_en", 1, 2),
0074 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "rg_apll2_d4_en", 1, 2),
0075 FACTOR(CLK_TOP_CLK26M, "clk26m_ck", "clk26m", 1, 1),
0076 FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "clk26m", 1, 2),
0077 FACTOR(CLK_TOP_MIPI_26M, "mipi_26m", "clk26m", 1, 1),
0078 FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1),
0079 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
0080 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1, 4),
0081 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1, 8),
0082 FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_ck", 1, 16),
0083 FACTOR(CLK_TOP_AHB_INFRA_D2, "ahb_infra_d2", "ahb_infra_sel", 1, 2),
0084 FACTOR(CLK_TOP_NFI1X, "nfi1x_ck", "nfi2x_pad_sel", 1, 2),
0085 FACTOR(CLK_TOP_ETH_D2, "eth_d2_ck", "eth_sel", 1, 2),
0086 };
0087
0088 static const char * const uart0_parents[] __initconst = {
0089 "clk26m_ck",
0090 "univpll_d24"
0091 };
0092
0093 static const char * const gfmux_emi1x_parents[] __initconst = {
0094 "clk26m_ck",
0095 "dmpll_ck"
0096 };
0097
0098 static const char * const emi_ddrphy_parents[] __initconst = {
0099 "gfmux_emi1x_sel",
0100 "gfmux_emi1x_sel"
0101 };
0102
0103 static const char * const ahb_infra_parents[] __initconst = {
0104 "clk_null",
0105 "clk26m_ck",
0106 "mainpll_d11",
0107 "clk_null",
0108 "mainpll_d12",
0109 "clk_null",
0110 "clk_null",
0111 "clk_null",
0112 "clk_null",
0113 "clk_null",
0114 "clk_null",
0115 "clk_null",
0116 "mainpll_d10"
0117 };
0118
0119 static const char * const csw_mux_mfg_parents[] __initconst = {
0120 "clk_null",
0121 "clk_null",
0122 "univpll_d3",
0123 "univpll_d2",
0124 "clk26m_ck",
0125 "mainpll_d4",
0126 "univpll_d24",
0127 "mmpll380m"
0128 };
0129
0130 static const char * const msdc0_parents[] __initconst = {
0131 "clk26m_ck",
0132 "univpll_d6",
0133 "mainpll_d8",
0134 "univpll_d8",
0135 "mainpll_d16",
0136 "mmpll_200m",
0137 "mainpll_d12",
0138 "mmpll_d2"
0139 };
0140
0141 static const char * const camtg_mm_parents[] __initconst = {
0142 "clk_null",
0143 "clk26m_ck",
0144 "usb_phy48m_ck",
0145 "clk_null",
0146 "univpll_d6"
0147 };
0148
0149 static const char * const pwm_mm_parents[] __initconst = {
0150 "clk26m_ck",
0151 "univpll_d12"
0152 };
0153
0154 static const char * const uart1_parents[] __initconst = {
0155 "clk26m_ck",
0156 "univpll_d24"
0157 };
0158
0159 static const char * const msdc1_parents[] __initconst = {
0160 "clk26m_ck",
0161 "univpll_d6",
0162 "mainpll_d8",
0163 "univpll_d8",
0164 "mainpll_d16",
0165 "mmpll_200m",
0166 "mainpll_d12",
0167 "mmpll_d2"
0168 };
0169
0170 static const char * const spm_52m_parents[] __initconst = {
0171 "clk26m_ck",
0172 "univpll_d24"
0173 };
0174
0175 static const char * const pmicspi_parents[] __initconst = {
0176 "univpll_d20",
0177 "usb_phy48m_ck",
0178 "univpll_d16",
0179 "clk26m_ck"
0180 };
0181
0182 static const char * const qaxi_aud26m_parents[] __initconst = {
0183 "clk26m_ck",
0184 "ahb_infra_sel"
0185 };
0186
0187 static const char * const aud_intbus_parents[] __initconst = {
0188 "clk_null",
0189 "clk26m_ck",
0190 "mainpll_d22",
0191 "clk_null",
0192 "mainpll_d11"
0193 };
0194
0195 static const char * const nfi2x_pad_parents[] __initconst = {
0196 "clk_null",
0197 "clk_null",
0198 "clk_null",
0199 "clk_null",
0200 "clk_null",
0201 "clk_null",
0202 "clk_null",
0203 "clk_null",
0204 "clk26m_ck",
0205 "clk_null",
0206 "clk_null",
0207 "clk_null",
0208 "clk_null",
0209 "clk_null",
0210 "clk_null",
0211 "clk_null",
0212 "clk_null",
0213 "mainpll_d12",
0214 "mainpll_d8",
0215 "clk_null",
0216 "mainpll_d6",
0217 "clk_null",
0218 "clk_null",
0219 "clk_null",
0220 "clk_null",
0221 "clk_null",
0222 "clk_null",
0223 "clk_null",
0224 "clk_null",
0225 "clk_null",
0226 "clk_null",
0227 "clk_null",
0228 "mainpll_d4",
0229 "clk_null",
0230 "clk_null",
0231 "clk_null",
0232 "clk_null",
0233 "clk_null",
0234 "clk_null",
0235 "clk_null",
0236 "clk_null",
0237 "clk_null",
0238 "clk_null",
0239 "clk_null",
0240 "clk_null",
0241 "clk_null",
0242 "clk_null",
0243 "clk_null",
0244 "clk_null",
0245 "clk_null",
0246 "clk_null",
0247 "clk_null",
0248 "clk_null",
0249 "clk_null",
0250 "clk_null",
0251 "clk_null",
0252 "clk_null",
0253 "clk_null",
0254 "clk_null",
0255 "clk_null",
0256 "clk_null",
0257 "clk_null",
0258 "clk_null",
0259 "clk_null",
0260 "clk_null",
0261 "clk_null",
0262 "clk_null",
0263 "clk_null",
0264 "clk_null",
0265 "clk_null",
0266 "clk_null",
0267 "clk_null",
0268 "clk_null",
0269 "clk_null",
0270 "clk_null",
0271 "clk_null",
0272 "clk_null",
0273 "clk_null",
0274 "clk_null",
0275 "clk_null",
0276 "clk_null",
0277 "mainpll_d10",
0278 "mainpll_d7",
0279 "clk_null",
0280 "mainpll_d5"
0281 };
0282
0283 static const char * const nfi1x_pad_parents[] __initconst = {
0284 "ahb_infra_sel",
0285 "nfi1x_ck"
0286 };
0287
0288 static const char * const mfg_mm_parents[] __initconst = {
0289 "clk_null",
0290 "clk_null",
0291 "clk_null",
0292 "clk_null",
0293 "clk_null",
0294 "clk_null",
0295 "clk_null",
0296 "clk_null",
0297 "csw_mux_mfg_sel",
0298 "clk_null",
0299 "clk_null",
0300 "clk_null",
0301 "clk_null",
0302 "clk_null",
0303 "clk_null",
0304 "clk_null",
0305 "mainpll_d3",
0306 "clk_null",
0307 "clk_null",
0308 "clk_null",
0309 "clk_null",
0310 "clk_null",
0311 "clk_null",
0312 "clk_null",
0313 "clk_null",
0314 "clk_null",
0315 "clk_null",
0316 "clk_null",
0317 "clk_null",
0318 "clk_null",
0319 "clk_null",
0320 "clk_null",
0321 "clk_null",
0322 "mainpll_d5",
0323 "mainpll_d7",
0324 "clk_null",
0325 "mainpll_d14"
0326 };
0327
0328 static const char * const ddrphycfg_parents[] __initconst = {
0329 "clk26m_ck",
0330 "mainpll_d16"
0331 };
0332
0333 static const char * const smi_mm_parents[] __initconst = {
0334 "clk26m_ck",
0335 "clk_null",
0336 "clk_null",
0337 "clk_null",
0338 "clk_null",
0339 "clk_null",
0340 "clk_null",
0341 "clk_null",
0342 "clk_null",
0343 "univpll_d4",
0344 "mainpll_d7",
0345 "clk_null",
0346 "mainpll_d14"
0347 };
0348
0349 static const char * const usb_78m_parents[] __initconst = {
0350 "clk_null",
0351 "clk26m_ck",
0352 "univpll_d16",
0353 "clk_null",
0354 "mainpll_d20"
0355 };
0356
0357 static const char * const scam_mm_parents[] __initconst = {
0358 "clk_null",
0359 "clk26m_ck",
0360 "mainpll_d14",
0361 "clk_null",
0362 "mainpll_d12"
0363 };
0364
0365 static const char * const spinor_parents[] __initconst = {
0366 "clk26m_d2",
0367 "clk26m_ck",
0368 "mainpll_d40",
0369 "univpll_d24",
0370 "univpll_d20",
0371 "mainpll_d20",
0372 "mainpll_d16",
0373 "univpll_d12"
0374 };
0375
0376 static const char * const msdc2_parents[] __initconst = {
0377 "clk26m_ck",
0378 "univpll_d6",
0379 "mainpll_d8",
0380 "univpll_d8",
0381 "mainpll_d16",
0382 "mmpll_200m",
0383 "mainpll_d12",
0384 "mmpll_d2"
0385 };
0386
0387 static const char * const eth_parents[] __initconst = {
0388 "clk26m_ck",
0389 "mainpll_d40",
0390 "univpll_d24",
0391 "univpll_d20",
0392 "mainpll_d20"
0393 };
0394
0395 static const char * const vdec_mm_parents[] __initconst = {
0396 "clk26m_ck",
0397 "univpll_d4",
0398 "mainpll_d4",
0399 "univpll_d5",
0400 "univpll_d6",
0401 "mainpll_d6"
0402 };
0403
0404 static const char * const dpi0_mm_parents[] __initconst = {
0405 "clk26m_ck",
0406 "lvdspll_ck",
0407 "lvdspll_d2",
0408 "lvdspll_d4",
0409 "lvdspll_d8"
0410 };
0411
0412 static const char * const dpi1_mm_parents[] __initconst = {
0413 "clk26m_ck",
0414 "tvdpll_d2",
0415 "tvdpll_d4",
0416 "tvdpll_d8",
0417 "tvdpll_d16"
0418 };
0419
0420 static const char * const axi_mfg_in_parents[] __initconst = {
0421 "clk26m_ck",
0422 "mainpll_d11",
0423 "univpll_d24",
0424 "mmpll380m"
0425 };
0426
0427 static const char * const slow_mfg_parents[] __initconst = {
0428 "clk26m_ck",
0429 "univpll_d12",
0430 "univpll_d24"
0431 };
0432
0433 static const char * const aud1_parents[] __initconst = {
0434 "clk26m_ck",
0435 "apll1_ck"
0436 };
0437
0438 static const char * const aud2_parents[] __initconst = {
0439 "clk26m_ck",
0440 "apll2_ck"
0441 };
0442
0443 static const char * const aud_engen1_parents[] __initconst = {
0444 "clk26m_ck",
0445 "rg_apll1_d2_en",
0446 "rg_apll1_d4_en",
0447 "rg_apll1_d8_en"
0448 };
0449
0450 static const char * const aud_engen2_parents[] __initconst = {
0451 "clk26m_ck",
0452 "rg_apll2_d2_en",
0453 "rg_apll2_d4_en",
0454 "rg_apll2_d8_en"
0455 };
0456
0457 static const char * const i2c_parents[] __initconst = {
0458 "clk26m_ck",
0459 "univpll_d20",
0460 "univpll_d16",
0461 "univpll_d12"
0462 };
0463
0464 static const char * const aud_i2s0_m_parents[] __initconst = {
0465 "rg_aud1",
0466 "rg_aud2"
0467 };
0468
0469 static const char * const pwm_parents[] __initconst = {
0470 "clk26m_ck",
0471 "univpll_d12"
0472 };
0473
0474 static const char * const spi_parents[] __initconst = {
0475 "clk26m_ck",
0476 "univpll_d12",
0477 "univpll_d8",
0478 "univpll_d6"
0479 };
0480
0481 static const char * const aud_spdifin_parents[] __initconst = {
0482 "clk26m_ck",
0483 "univpll_d2"
0484 };
0485
0486 static const char * const uart2_parents[] __initconst = {
0487 "clk26m_ck",
0488 "univpll_d24"
0489 };
0490
0491 static const char * const bsi_parents[] __initconst = {
0492 "clk26m_ck",
0493 "mainpll_d10",
0494 "mainpll_d12",
0495 "mainpll_d20"
0496 };
0497
0498 static const char * const dbg_atclk_parents[] __initconst = {
0499 "clk_null",
0500 "clk26m_ck",
0501 "mainpll_d5",
0502 "clk_null",
0503 "univpll_d5"
0504 };
0505
0506 static const char * const csw_nfiecc_parents[] __initconst = {
0507 "clk_null",
0508 "mainpll_d7",
0509 "mainpll_d6",
0510 "clk_null",
0511 "mainpll_d5"
0512 };
0513
0514 static const char * const nfiecc_parents[] __initconst = {
0515 "clk_null",
0516 "nfi2x_pad_sel",
0517 "mainpll_d4",
0518 "clk_null",
0519 "csw_nfiecc_sel"
0520 };
0521
0522 static struct mtk_composite top_muxes[] __initdata = {
0523
0524 MUX(CLK_TOP_UART0_SEL, "uart0_sel", uart0_parents,
0525 0x000, 0, 1),
0526 MUX(CLK_TOP_GFMUX_EMI1X_SEL, "gfmux_emi1x_sel", gfmux_emi1x_parents,
0527 0x000, 1, 1),
0528 MUX(CLK_TOP_EMI_DDRPHY_SEL, "emi_ddrphy_sel", emi_ddrphy_parents,
0529 0x000, 2, 1),
0530 MUX(CLK_TOP_AHB_INFRA_SEL, "ahb_infra_sel", ahb_infra_parents,
0531 0x000, 4, 4),
0532 MUX(CLK_TOP_CSW_MUX_MFG_SEL, "csw_mux_mfg_sel", csw_mux_mfg_parents,
0533 0x000, 8, 3),
0534 MUX(CLK_TOP_MSDC0_SEL, "msdc0_sel", msdc0_parents,
0535 0x000, 11, 3),
0536 MUX(CLK_TOP_CAMTG_MM_SEL, "camtg_mm_sel", camtg_mm_parents,
0537 0x000, 15, 3),
0538 MUX(CLK_TOP_PWM_MM_SEL, "pwm_mm_sel", pwm_mm_parents,
0539 0x000, 18, 1),
0540 MUX(CLK_TOP_UART1_SEL, "uart1_sel", uart1_parents,
0541 0x000, 19, 1),
0542 MUX(CLK_TOP_MSDC1_SEL, "msdc1_sel", msdc1_parents,
0543 0x000, 20, 3),
0544 MUX(CLK_TOP_SPM_52M_SEL, "spm_52m_sel", spm_52m_parents,
0545 0x000, 23, 1),
0546 MUX(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
0547 0x000, 24, 2),
0548 MUX(CLK_TOP_QAXI_AUD26M_SEL, "qaxi_aud26m_sel", qaxi_aud26m_parents,
0549 0x000, 26, 1),
0550 MUX(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
0551 0x000, 27, 3),
0552
0553 MUX(CLK_TOP_NFI2X_PAD_SEL, "nfi2x_pad_sel", nfi2x_pad_parents,
0554 0x004, 0, 7),
0555 MUX(CLK_TOP_NFI1X_PAD_SEL, "nfi1x_pad_sel", nfi1x_pad_parents,
0556 0x004, 7, 1),
0557 MUX(CLK_TOP_MFG_MM_SEL, "mfg_mm_sel", mfg_mm_parents,
0558 0x004, 8, 6),
0559 MUX(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
0560 0x004, 15, 1),
0561 MUX(CLK_TOP_SMI_MM_SEL, "smi_mm_sel", smi_mm_parents,
0562 0x004, 16, 4),
0563 MUX(CLK_TOP_USB_78M_SEL, "usb_78m_sel", usb_78m_parents,
0564 0x004, 20, 3),
0565 MUX(CLK_TOP_SCAM_MM_SEL, "scam_mm_sel", scam_mm_parents,
0566 0x004, 23, 3),
0567
0568 MUX(CLK_TOP_SPINOR_SEL, "spinor_sel", spinor_parents,
0569 0x040, 0, 3),
0570 MUX(CLK_TOP_MSDC2_SEL, "msdc2_sel", msdc2_parents,
0571 0x040, 3, 3),
0572 MUX(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
0573 0x040, 6, 3),
0574 MUX(CLK_TOP_VDEC_MM_SEL, "vdec_mm_sel", vdec_mm_parents,
0575 0x040, 9, 3),
0576 MUX(CLK_TOP_DPI0_MM_SEL, "dpi0_mm_sel", dpi0_mm_parents,
0577 0x040, 12, 3),
0578 MUX(CLK_TOP_DPI1_MM_SEL, "dpi1_mm_sel", dpi1_mm_parents,
0579 0x040, 15, 3),
0580 MUX(CLK_TOP_AXI_MFG_IN_SEL, "axi_mfg_in_sel", axi_mfg_in_parents,
0581 0x040, 18, 2),
0582 MUX(CLK_TOP_SLOW_MFG_SEL, "slow_mfg_sel", slow_mfg_parents,
0583 0x040, 20, 2),
0584 MUX(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
0585 0x040, 22, 1),
0586 MUX(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
0587 0x040, 23, 1),
0588 MUX(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", aud_engen1_parents,
0589 0x040, 24, 2),
0590 MUX(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", aud_engen2_parents,
0591 0x040, 26, 2),
0592 MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
0593 0x040, 28, 2),
0594
0595 MUX(CLK_TOP_AUD_I2S0_M_SEL, "aud_i2s0_m_sel", aud_i2s0_m_parents,
0596 0x044, 12, 1),
0597 MUX(CLK_TOP_AUD_I2S1_M_SEL, "aud_i2s1_m_sel", aud_i2s0_m_parents,
0598 0x044, 13, 1),
0599 MUX(CLK_TOP_AUD_I2S2_M_SEL, "aud_i2s2_m_sel", aud_i2s0_m_parents,
0600 0x044, 14, 1),
0601 MUX(CLK_TOP_AUD_I2S3_M_SEL, "aud_i2s3_m_sel", aud_i2s0_m_parents,
0602 0x044, 15, 1),
0603 MUX(CLK_TOP_AUD_I2S4_M_SEL, "aud_i2s4_m_sel", aud_i2s0_m_parents,
0604 0x044, 16, 1),
0605 MUX(CLK_TOP_AUD_I2S5_M_SEL, "aud_i2s5_m_sel", aud_i2s0_m_parents,
0606 0x044, 17, 1),
0607 MUX(CLK_TOP_AUD_SPDIF_B_SEL, "aud_spdif_b_sel", aud_i2s0_m_parents,
0608 0x044, 18, 1),
0609
0610 MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
0611 0x07c, 0, 1),
0612 MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
0613 0x07c, 1, 2),
0614 MUX(CLK_TOP_AUD_SPDIFIN_SEL, "aud_spdifin_sel", aud_spdifin_parents,
0615 0x07c, 3, 1),
0616 MUX(CLK_TOP_UART2_SEL, "uart2_sel", uart2_parents,
0617 0x07c, 4, 1),
0618 MUX(CLK_TOP_BSI_SEL, "bsi_sel", bsi_parents,
0619 0x07c, 5, 2),
0620 MUX(CLK_TOP_DBG_ATCLK_SEL, "dbg_atclk_sel", dbg_atclk_parents,
0621 0x07c, 7, 3),
0622 MUX(CLK_TOP_CSW_NFIECC_SEL, "csw_nfiecc_sel", csw_nfiecc_parents,
0623 0x07c, 10, 3),
0624 MUX(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents,
0625 0x07c, 13, 3),
0626 };
0627
0628 static const char * const ifr_mux1_parents[] __initconst = {
0629 "clk26m_ck",
0630 "armpll",
0631 "univpll",
0632 "mainpll_d2"
0633 };
0634
0635 static const char * const ifr_eth_25m_parents[] __initconst = {
0636 "eth_d2_ck",
0637 "rg_eth"
0638 };
0639
0640 static const char * const ifr_i2c0_parents[] __initconst = {
0641 "ahb_infra_d2",
0642 "rg_i2c"
0643 };
0644
0645 static const struct mtk_composite ifr_muxes[] __initconst = {
0646 MUX(CLK_IFR_MUX1_SEL, "ifr_mux1_sel", ifr_mux1_parents, 0x000,
0647 2, 2),
0648 MUX(CLK_IFR_ETH_25M_SEL, "ifr_eth_25m_sel", ifr_eth_25m_parents, 0x080,
0649 0, 1),
0650 MUX(CLK_IFR_I2C0_SEL, "ifr_i2c0_sel", ifr_i2c0_parents, 0x080,
0651 1, 1),
0652 MUX(CLK_IFR_I2C1_SEL, "ifr_i2c1_sel", ifr_i2c0_parents, 0x080,
0653 2, 1),
0654 MUX(CLK_IFR_I2C2_SEL, "ifr_i2c2_sel", ifr_i2c0_parents, 0x080,
0655 3, 1),
0656 };
0657
0658 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \
0659 .id = _id, \
0660 .name = _name, \
0661 .parent_name = _parent, \
0662 .div_reg = _reg, \
0663 .div_shift = _shift, \
0664 .div_width = _width, \
0665 }
0666
0667 static const struct mtk_clk_divider top_adj_divs[] = {
0668 DIV_ADJ(CLK_TOP_APLL12_CK_DIV0, "apll12_ck_div0", "aud_i2s0_m_sel",
0669 0x0048, 0, 8),
0670 DIV_ADJ(CLK_TOP_APLL12_CK_DIV1, "apll12_ck_div1", "aud_i2s1_m_sel",
0671 0x0048, 8, 8),
0672 DIV_ADJ(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "aud_i2s2_m_sel",
0673 0x0048, 16, 8),
0674 DIV_ADJ(CLK_TOP_APLL12_CK_DIV3, "apll12_ck_div3", "aud_i2s3_m_sel",
0675 0x0048, 24, 8),
0676 DIV_ADJ(CLK_TOP_APLL12_CK_DIV4, "apll12_ck_div4", "aud_i2s4_m_sel",
0677 0x004c, 0, 8),
0678 DIV_ADJ(CLK_TOP_APLL12_CK_DIV4B, "apll12_ck_div4b", "apll12_div4",
0679 0x004c, 8, 8),
0680 DIV_ADJ(CLK_TOP_APLL12_CK_DIV5, "apll12_ck_div5", "aud_i2s5_m_sel",
0681 0x004c, 16, 8),
0682 DIV_ADJ(CLK_TOP_APLL12_CK_DIV5B, "apll12_ck_div5b", "apll12_div5",
0683 0x004c, 24, 8),
0684 DIV_ADJ(CLK_TOP_APLL12_CK_DIV6, "apll12_ck_div6", "aud_spdif_b_sel",
0685 0x0078, 0, 8),
0686 };
0687
0688 #define DIV_ADJ_FLAG(_id, _name, _parent, _reg, _shift, _width, _flag) { \
0689 .id = _id, \
0690 .name = _name, \
0691 .parent_name = _parent, \
0692 .div_reg = _reg, \
0693 .div_shift = _shift, \
0694 .div_width = _width, \
0695 .clk_divider_flags = _flag, \
0696 }
0697
0698 static const struct mtk_clk_divider apmixed_adj_divs[] = {
0699 DIV_ADJ_FLAG(CLK_APMIXED_HDMI_REF, "hdmi_ref", "tvdpll",
0700 0x1c4, 24, 3, CLK_DIVIDER_POWER_OF_TWO),
0701 };
0702
0703 static const struct mtk_gate_regs top0_cg_regs = {
0704 .set_ofs = 0x50,
0705 .clr_ofs = 0x80,
0706 .sta_ofs = 0x20,
0707 };
0708
0709 static const struct mtk_gate_regs top1_cg_regs = {
0710 .set_ofs = 0x54,
0711 .clr_ofs = 0x84,
0712 .sta_ofs = 0x24,
0713 };
0714
0715 static const struct mtk_gate_regs top2_cg_regs = {
0716 .set_ofs = 0x6c,
0717 .clr_ofs = 0x9c,
0718 .sta_ofs = 0x3c,
0719 };
0720
0721 static const struct mtk_gate_regs top3_cg_regs = {
0722 .set_ofs = 0xa0,
0723 .clr_ofs = 0xb0,
0724 .sta_ofs = 0x70,
0725 };
0726
0727 static const struct mtk_gate_regs top4_cg_regs = {
0728 .set_ofs = 0xa4,
0729 .clr_ofs = 0xb4,
0730 .sta_ofs = 0x74,
0731 };
0732
0733 static const struct mtk_gate_regs top5_cg_regs = {
0734 .set_ofs = 0x44,
0735 .clr_ofs = 0x44,
0736 .sta_ofs = 0x44,
0737 };
0738
0739 #define GATE_TOP0(_id, _name, _parent, _shift) { \
0740 .id = _id, \
0741 .name = _name, \
0742 .parent_name = _parent, \
0743 .regs = &top0_cg_regs, \
0744 .shift = _shift, \
0745 .ops = &mtk_clk_gate_ops_setclr, \
0746 }
0747
0748 #define GATE_TOP0_I(_id, _name, _parent, _shift) { \
0749 .id = _id, \
0750 .name = _name, \
0751 .parent_name = _parent, \
0752 .regs = &top0_cg_regs, \
0753 .shift = _shift, \
0754 .ops = &mtk_clk_gate_ops_setclr_inv, \
0755 }
0756
0757 #define GATE_TOP1(_id, _name, _parent, _shift) { \
0758 .id = _id, \
0759 .name = _name, \
0760 .parent_name = _parent, \
0761 .regs = &top1_cg_regs, \
0762 .shift = _shift, \
0763 .ops = &mtk_clk_gate_ops_setclr, \
0764 }
0765
0766 #define GATE_TOP2(_id, _name, _parent, _shift) { \
0767 .id = _id, \
0768 .name = _name, \
0769 .parent_name = _parent, \
0770 .regs = &top2_cg_regs, \
0771 .shift = _shift, \
0772 .ops = &mtk_clk_gate_ops_setclr, \
0773 }
0774
0775 #define GATE_TOP2_I(_id, _name, _parent, _shift) { \
0776 .id = _id, \
0777 .name = _name, \
0778 .parent_name = _parent, \
0779 .regs = &top2_cg_regs, \
0780 .shift = _shift, \
0781 .ops = &mtk_clk_gate_ops_setclr_inv, \
0782 }
0783
0784 #define GATE_TOP3(_id, _name, _parent, _shift) { \
0785 .id = _id, \
0786 .name = _name, \
0787 .parent_name = _parent, \
0788 .regs = &top3_cg_regs, \
0789 .shift = _shift, \
0790 .ops = &mtk_clk_gate_ops_setclr, \
0791 }
0792
0793 #define GATE_TOP4_I(_id, _name, _parent, _shift) { \
0794 .id = _id, \
0795 .name = _name, \
0796 .parent_name = _parent, \
0797 .regs = &top4_cg_regs, \
0798 .shift = _shift, \
0799 .ops = &mtk_clk_gate_ops_setclr_inv, \
0800 }
0801
0802 #define GATE_TOP5(_id, _name, _parent, _shift) { \
0803 .id = _id, \
0804 .name = _name, \
0805 .parent_name = _parent, \
0806 .regs = &top5_cg_regs, \
0807 .shift = _shift, \
0808 .ops = &mtk_clk_gate_ops_no_setclr, \
0809 }
0810
0811 static const struct mtk_gate top_clks[] __initconst = {
0812
0813 GATE_TOP0(CLK_TOP_PWM_MM, "pwm_mm", "pwm_mm_sel", 0),
0814 GATE_TOP0(CLK_TOP_CAM_MM, "cam_mm", "camtg_mm_sel", 1),
0815 GATE_TOP0(CLK_TOP_MFG_MM, "mfg_mm", "mfg_mm_sel", 2),
0816 GATE_TOP0(CLK_TOP_SPM_52M, "spm_52m", "spm_52m_sel", 3),
0817 GATE_TOP0_I(CLK_TOP_MIPI_26M_DBG, "mipi_26m_dbg", "mipi_26m", 4),
0818 GATE_TOP0(CLK_TOP_SCAM_MM, "scam_mm", "scam_mm_sel", 5),
0819 GATE_TOP0(CLK_TOP_SMI_MM, "smi_mm", "smi_mm_sel", 9),
0820
0821 GATE_TOP1(CLK_TOP_THEM, "them", "ahb_infra_sel", 1),
0822 GATE_TOP1(CLK_TOP_APDMA, "apdma", "ahb_infra_sel", 2),
0823 GATE_TOP1(CLK_TOP_I2C0, "i2c0", "ifr_i2c0_sel", 3),
0824 GATE_TOP1(CLK_TOP_I2C1, "i2c1", "ifr_i2c1_sel", 4),
0825 GATE_TOP1(CLK_TOP_AUXADC1, "auxadc1", "ahb_infra_sel", 5),
0826 GATE_TOP1(CLK_TOP_NFI, "nfi", "nfi1x_pad_sel", 6),
0827 GATE_TOP1(CLK_TOP_NFIECC, "nfiecc", "rg_nfiecc", 7),
0828 GATE_TOP1(CLK_TOP_DEBUGSYS, "debugsys", "rg_dbg_atclk", 8),
0829 GATE_TOP1(CLK_TOP_PWM, "pwm", "ahb_infra_sel", 9),
0830 GATE_TOP1(CLK_TOP_UART0, "uart0", "uart0_sel", 10),
0831 GATE_TOP1(CLK_TOP_UART1, "uart1", "uart1_sel", 11),
0832 GATE_TOP1(CLK_TOP_BTIF, "btif", "ahb_infra_sel", 12),
0833 GATE_TOP1(CLK_TOP_USB, "usb", "usb_78m", 13),
0834 GATE_TOP1(CLK_TOP_FLASHIF_26M, "flashif_26m", "clk26m_ck", 14),
0835 GATE_TOP1(CLK_TOP_AUXADC2, "auxadc2", "ahb_infra_sel", 15),
0836 GATE_TOP1(CLK_TOP_I2C2, "i2c2", "ifr_i2c2_sel", 16),
0837 GATE_TOP1(CLK_TOP_MSDC0, "msdc0", "msdc0_sel", 17),
0838 GATE_TOP1(CLK_TOP_MSDC1, "msdc1", "msdc1_sel", 18),
0839 GATE_TOP1(CLK_TOP_NFI2X, "nfi2x", "nfi2x_pad_sel", 19),
0840 GATE_TOP1(CLK_TOP_PMICWRAP_AP, "pwrap_ap", "clk26m_ck", 20),
0841 GATE_TOP1(CLK_TOP_SEJ, "sej", "ahb_infra_sel", 21),
0842 GATE_TOP1(CLK_TOP_MEMSLP_DLYER, "memslp_dlyer", "clk26m_ck", 22),
0843 GATE_TOP1(CLK_TOP_SPI, "spi", "spi_sel", 23),
0844 GATE_TOP1(CLK_TOP_APXGPT, "apxgpt", "clk26m_ck", 24),
0845 GATE_TOP1(CLK_TOP_AUDIO, "audio", "clk26m_ck", 25),
0846 GATE_TOP1(CLK_TOP_PMICWRAP_MD, "pwrap_md", "clk26m_ck", 27),
0847 GATE_TOP1(CLK_TOP_PMICWRAP_CONN, "pwrap_conn", "clk26m_ck", 28),
0848 GATE_TOP1(CLK_TOP_PMICWRAP_26M, "pwrap_26m", "clk26m_ck", 29),
0849 GATE_TOP1(CLK_TOP_AUX_ADC, "aux_adc", "clk26m_ck", 30),
0850 GATE_TOP1(CLK_TOP_AUX_TP, "aux_tp", "clk26m_ck", 31),
0851
0852 GATE_TOP2(CLK_TOP_MSDC2, "msdc2", "ahb_infra_sel", 0),
0853 GATE_TOP2(CLK_TOP_RBIST, "rbist", "univpll_d12", 1),
0854 GATE_TOP2(CLK_TOP_NFI_BUS, "nfi_bus", "ahb_infra_sel", 2),
0855 GATE_TOP2(CLK_TOP_GCE, "gce", "ahb_infra_sel", 4),
0856 GATE_TOP2(CLK_TOP_TRNG, "trng", "ahb_infra_sel", 5),
0857 GATE_TOP2(CLK_TOP_SEJ_13M, "sej_13m", "clk26m_ck", 6),
0858 GATE_TOP2(CLK_TOP_AES, "aes", "ahb_infra_sel", 7),
0859 GATE_TOP2(CLK_TOP_PWM_B, "pwm_b", "rg_pwm_infra", 8),
0860 GATE_TOP2(CLK_TOP_PWM1_FB, "pwm1_fb", "rg_pwm_infra", 9),
0861 GATE_TOP2(CLK_TOP_PWM2_FB, "pwm2_fb", "rg_pwm_infra", 10),
0862 GATE_TOP2(CLK_TOP_PWM3_FB, "pwm3_fb", "rg_pwm_infra", 11),
0863 GATE_TOP2(CLK_TOP_PWM4_FB, "pwm4_fb", "rg_pwm_infra", 12),
0864 GATE_TOP2(CLK_TOP_PWM5_FB, "pwm5_fb", "rg_pwm_infra", 13),
0865 GATE_TOP2(CLK_TOP_USB_1P, "usb_1p", "usb_78m", 14),
0866 GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, "flashif_freerun", "ahb_infra_sel",
0867 15),
0868 GATE_TOP2(CLK_TOP_26M_HDMI_SIFM, "hdmi_sifm_26m", "clk26m_ck", 16),
0869 GATE_TOP2(CLK_TOP_26M_CEC, "cec_26m", "clk26m_ck", 17),
0870 GATE_TOP2(CLK_TOP_32K_CEC, "cec_32k", "clk32k", 18),
0871 GATE_TOP2(CLK_TOP_66M_ETH, "eth_66m", "ahb_infra_d2", 19),
0872 GATE_TOP2(CLK_TOP_133M_ETH, "eth_133m", "ahb_infra_sel", 20),
0873 GATE_TOP2(CLK_TOP_FETH_25M, "feth_25m", "ifr_eth_25m_sel", 21),
0874 GATE_TOP2(CLK_TOP_FETH_50M, "feth_50m", "rg_eth", 22),
0875 GATE_TOP2(CLK_TOP_FLASHIF_AXI, "flashif_axi", "ahb_infra_sel", 23),
0876 GATE_TOP2(CLK_TOP_USBIF, "usbif", "ahb_infra_sel", 24),
0877 GATE_TOP2(CLK_TOP_UART2, "uart2", "rg_uart2", 25),
0878 GATE_TOP2(CLK_TOP_BSI, "bsi", "ahb_infra_sel", 26),
0879 GATE_TOP2(CLK_TOP_GCPU_B, "gcpu_b", "ahb_infra_sel", 27),
0880 GATE_TOP2_I(CLK_TOP_MSDC0_INFRA, "msdc0_infra", "msdc0", 28),
0881 GATE_TOP2_I(CLK_TOP_MSDC1_INFRA, "msdc1_infra", "msdc1", 29),
0882 GATE_TOP2_I(CLK_TOP_MSDC2_INFRA, "msdc2_infra", "rg_msdc2", 30),
0883 GATE_TOP2(CLK_TOP_USB_78M, "usb_78m", "usb_78m_sel", 31),
0884
0885 GATE_TOP3(CLK_TOP_RG_SPINOR, "rg_spinor", "spinor_sel", 0),
0886 GATE_TOP3(CLK_TOP_RG_MSDC2, "rg_msdc2", "msdc2_sel", 1),
0887 GATE_TOP3(CLK_TOP_RG_ETH, "rg_eth", "eth_sel", 2),
0888 GATE_TOP3(CLK_TOP_RG_VDEC, "rg_vdec", "vdec_mm_sel", 3),
0889 GATE_TOP3(CLK_TOP_RG_FDPI0, "rg_fdpi0", "dpi0_mm_sel", 4),
0890 GATE_TOP3(CLK_TOP_RG_FDPI1, "rg_fdpi1", "dpi1_mm_sel", 5),
0891 GATE_TOP3(CLK_TOP_RG_AXI_MFG, "rg_axi_mfg", "axi_mfg_in_sel", 6),
0892 GATE_TOP3(CLK_TOP_RG_SLOW_MFG, "rg_slow_mfg", "slow_mfg_sel", 7),
0893 GATE_TOP3(CLK_TOP_RG_AUD1, "rg_aud1", "aud1_sel", 8),
0894 GATE_TOP3(CLK_TOP_RG_AUD2, "rg_aud2", "aud2_sel", 9),
0895 GATE_TOP3(CLK_TOP_RG_AUD_ENGEN1, "rg_aud_engen1", "aud_engen1_sel", 10),
0896 GATE_TOP3(CLK_TOP_RG_AUD_ENGEN2, "rg_aud_engen2", "aud_engen2_sel", 11),
0897 GATE_TOP3(CLK_TOP_RG_I2C, "rg_i2c", "i2c_sel", 12),
0898 GATE_TOP3(CLK_TOP_RG_PWM_INFRA, "rg_pwm_infra", "pwm_sel", 13),
0899 GATE_TOP3(CLK_TOP_RG_AUD_SPDIF_IN, "rg_aud_spdif_in", "aud_spdifin_sel",
0900 14),
0901 GATE_TOP3(CLK_TOP_RG_UART2, "rg_uart2", "uart2_sel", 15),
0902 GATE_TOP3(CLK_TOP_RG_BSI, "rg_bsi", "bsi_sel", 16),
0903 GATE_TOP3(CLK_TOP_RG_DBG_ATCLK, "rg_dbg_atclk", "dbg_atclk_sel", 17),
0904 GATE_TOP3(CLK_TOP_RG_NFIECC, "rg_nfiecc", "nfiecc_sel", 18),
0905
0906 GATE_TOP4_I(CLK_TOP_RG_APLL1_D2_EN, "rg_apll1_d2_en", "apll1_d2", 8),
0907 GATE_TOP4_I(CLK_TOP_RG_APLL1_D4_EN, "rg_apll1_d4_en", "apll1_d4", 9),
0908 GATE_TOP4_I(CLK_TOP_RG_APLL1_D8_EN, "rg_apll1_d8_en", "apll1_d8", 10),
0909 GATE_TOP4_I(CLK_TOP_RG_APLL2_D2_EN, "rg_apll2_d2_en", "apll2_d2", 11),
0910 GATE_TOP4_I(CLK_TOP_RG_APLL2_D4_EN, "rg_apll2_d4_en", "apll2_d4", 12),
0911 GATE_TOP4_I(CLK_TOP_RG_APLL2_D8_EN, "rg_apll2_d8_en", "apll2_d8", 13),
0912
0913 GATE_TOP5(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll12_ck_div0", 0),
0914 GATE_TOP5(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll12_ck_div1", 1),
0915 GATE_TOP5(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll12_ck_div2", 2),
0916 GATE_TOP5(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll12_ck_div3", 3),
0917 GATE_TOP5(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll12_ck_div4", 4),
0918 GATE_TOP5(CLK_TOP_APLL12_DIV4B, "apll12_div4b", "apll12_ck_div4b", 5),
0919 GATE_TOP5(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll12_ck_div5", 6),
0920 GATE_TOP5(CLK_TOP_APLL12_DIV5B, "apll12_div5b", "apll12_ck_div5b", 7),
0921 GATE_TOP5(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll12_ck_div6", 8),
0922 };
0923
0924 static void __init mtk_topckgen_init(struct device_node *node)
0925 {
0926 struct clk_hw_onecell_data *clk_data;
0927 int r;
0928 void __iomem *base;
0929
0930 base = of_iomap(node, 0);
0931 if (!base) {
0932 pr_err("%s(): ioremap failed\n", __func__);
0933 return;
0934 }
0935
0936 clk_data = mtk_alloc_clk_data(MT8167_CLK_TOP_NR_CLK);
0937
0938 mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks),
0939 clk_data);
0940 mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), clk_data);
0941
0942 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
0943 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
0944 &mt8167_clk_lock, clk_data);
0945 mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
0946 base, &mt8167_clk_lock, clk_data);
0947
0948 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0949 if (r)
0950 pr_err("%s(): could not register clock provider: %d\n",
0951 __func__, r);
0952 }
0953 CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8167-topckgen", mtk_topckgen_init);
0954
0955 static void __init mtk_infracfg_init(struct device_node *node)
0956 {
0957 struct clk_hw_onecell_data *clk_data;
0958 int r;
0959 void __iomem *base;
0960
0961 base = of_iomap(node, 0);
0962 if (!base) {
0963 pr_err("%s(): ioremap failed\n", __func__);
0964 return;
0965 }
0966
0967 clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK);
0968
0969 mtk_clk_register_composites(ifr_muxes, ARRAY_SIZE(ifr_muxes), base,
0970 &mt8167_clk_lock, clk_data);
0971
0972 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0973 if (r)
0974 pr_err("%s(): could not register clock provider: %d\n",
0975 __func__, r);
0976 }
0977 CLK_OF_DECLARE(mtk_infracfg, "mediatek,mt8167-infracfg", mtk_infracfg_init);
0978
0979 #define MT8167_PLL_FMAX (2500UL * MHZ)
0980
0981 #define CON0_MT8167_RST_BAR BIT(27)
0982
0983 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
0984 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
0985 _pcw_shift, _div_table) { \
0986 .id = _id, \
0987 .name = _name, \
0988 .reg = _reg, \
0989 .pwr_reg = _pwr_reg, \
0990 .en_mask = _en_mask, \
0991 .flags = _flags, \
0992 .rst_bar_mask = CON0_MT8167_RST_BAR, \
0993 .fmax = MT8167_PLL_FMAX, \
0994 .pcwbits = _pcwbits, \
0995 .pd_reg = _pd_reg, \
0996 .pd_shift = _pd_shift, \
0997 .tuner_reg = _tuner_reg, \
0998 .pcw_reg = _pcw_reg, \
0999 .pcw_shift = _pcw_shift, \
1000 .div_table = _div_table, \
1001 }
1002
1003 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
1004 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
1005 _pcw_shift) \
1006 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
1007 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
1008 NULL)
1009
1010 static const struct mtk_pll_div_table mmpll_div_table[] = {
1011 { .div = 0, .freq = MT8167_PLL_FMAX },
1012 { .div = 1, .freq = 1000000000 },
1013 { .div = 2, .freq = 604500000 },
1014 { .div = 3, .freq = 253500000 },
1015 { .div = 4, .freq = 126750000 },
1016 { }
1017 };
1018
1019 static const struct mtk_pll_data plls[] = {
1020 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0, 0,
1021 21, 0x0104, 24, 0, 0x0104, 0),
1022 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0,
1023 HAVE_RST_BAR, 21, 0x0124, 24, 0, 0x0124, 0),
1024 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000000,
1025 HAVE_RST_BAR, 7, 0x0144, 24, 0, 0x0144, 0),
1026 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0, 0,
1027 21, 0x0164, 24, 0, 0x0164, 0, mmpll_div_table),
1028 PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0, 0,
1029 31, 0x0180, 1, 0x0194, 0x0184, 0),
1030 PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0, 0,
1031 31, 0x01A0, 1, 0x01B4, 0x01A4, 0),
1032 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x01C0, 0x01D0, 0, 0,
1033 21, 0x01C4, 24, 0, 0x01C4, 0),
1034 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x01E0, 0x01F0, 0, 0,
1035 21, 0x01E4, 24, 0, 0x01E4, 0),
1036 };
1037
1038 static void __init mtk_apmixedsys_init(struct device_node *node)
1039 {
1040 struct clk_hw_onecell_data *clk_data;
1041 void __iomem *base;
1042 int r;
1043
1044 base = of_iomap(node, 0);
1045 if (!base) {
1046 pr_err("%s(): ioremap failed\n", __func__);
1047 return;
1048 }
1049
1050 clk_data = mtk_alloc_clk_data(MT8167_CLK_APMIXED_NR_CLK);
1051
1052 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
1053 mtk_clk_register_dividers(apmixed_adj_divs, ARRAY_SIZE(apmixed_adj_divs),
1054 base, &mt8167_clk_lock, clk_data);
1055
1056 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1057 if (r)
1058 pr_err("%s(): could not register clock provider: %d\n",
1059 __func__, r);
1060
1061 }
1062 CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8167-apmixedsys",
1063 mtk_apmixedsys_init);
