clk/mediatek/clk-mt8167-mm.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2020 MediaTek Inc.
0004  * Copyright (c) 2020 BayLibre, SAS
0005  * Author: James Liao <jamesjj.liao@mediatek.com>
0006  *         Fabien Parent <fparent@baylibre.com>
0007  */
0008
0009 #include <linux/clk-provider.h>
0010 #include <linux/of.h>
0011 #include <linux/of_address.h>
0012 #include <linux/of_device.h>
0013 #include <linux/platform_device.h>
0014
0015 #include "clk-mtk.h"
0016 #include "clk-gate.h"
0017
0018 #include <dt-bindings/clock/mt8167-clk.h>
0019
0020 static const struct mtk_gate_regs mm0_cg_regs = {
0021     .set_ofs = 0x104,
0022     .clr_ofs = 0x108,
0023     .sta_ofs = 0x100,
0024 };
0025
0026 static const struct mtk_gate_regs mm1_cg_regs = {
0027     .set_ofs = 0x114,
0028     .clr_ofs = 0x118,
0029     .sta_ofs = 0x110,
0030 };
0031
0032 #define GATE_MM0(_id, _name, _parent, _shift) {     \
0033         .id = _id,              \
0034         .name = _name,              \
0035         .parent_name = _parent,         \
0036         .regs = &mm0_cg_regs,           \
0037         .shift = _shift,            \
0038         .ops = &mtk_clk_gate_ops_setclr,    \
0039     }
0040
0041 #define GATE_MM1(_id, _name, _parent, _shift) {     \
0042         .id = _id,              \
0043         .name = _name,              \
0044         .parent_name = _parent,         \
0045         .regs = &mm1_cg_regs,           \
0046         .shift = _shift,            \
0047         .ops = &mtk_clk_gate_ops_setclr,    \
0048     }
0049
0050 static const struct mtk_gate mm_clks[] = {
0051     /* MM0 */
0052     GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "smi_mm", 0),
0053     GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "smi_mm", 1),
0054     GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "smi_mm", 2),
0055     GATE_MM0(CLK_MM_MDP_RDMA, "mm_mdp_rdma", "smi_mm", 3),
0056     GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "smi_mm", 4),
0057     GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "smi_mm", 5),
0058     GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "smi_mm", 6),
0059     GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "smi_mm", 7),
0060     GATE_MM0(CLK_MM_MDP_WROT, "mm_mdp_wrot", "smi_mm", 8),
0061     GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "smi_mm", 9),
0062     GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "smi_mm", 10),
0063     GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "smi_mm", 11),
0064     GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "smi_mm", 12),
0065     GATE_MM0(CLK_MM_DISP_WDMA, "mm_disp_wdma", "smi_mm", 13),
0066     GATE_MM0(CLK_MM_DISP_COLOR, "mm_disp_color", "smi_mm", 14),
0067     GATE_MM0(CLK_MM_DISP_CCORR, "mm_disp_ccorr", "smi_mm", 15),
0068     GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "smi_mm", 16),
0069     GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "smi_mm", 17),
0070     GATE_MM0(CLK_MM_DISP_DITHER, "mm_disp_dither", "smi_mm", 18),
0071     GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "smi_mm", 19),
0072     /* MM1 */
0073     GATE_MM1(CLK_MM_DISP_PWM_MM, "mm_disp_pwm_mm", "smi_mm", 0),
0074     GATE_MM1(CLK_MM_DISP_PWM_26M, "mm_disp_pwm_26m", "smi_mm", 1),
0075     GATE_MM1(CLK_MM_DSI_ENGINE, "mm_dsi_engine", "smi_mm", 2),
0076     GATE_MM1(CLK_MM_DSI_DIGITAL, "mm_dsi_digital", "dsi0_lntc_dsick", 3),
0077     GATE_MM1(CLK_MM_DPI0_ENGINE, "mm_dpi0_engine", "smi_mm", 4),
0078     GATE_MM1(CLK_MM_DPI0_PXL, "mm_dpi0_pxl", "rg_fdpi0", 5),
0079     GATE_MM1(CLK_MM_LVDS_PXL, "mm_lvds_pxl", "vpll_dpix", 14),
0080     GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvdstx_dig_cts", 15),
0081     GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "smi_mm", 16),
0082     GATE_MM1(CLK_MM_DPI1_PXL, "mm_dpi1_pxl", "rg_fdpi1", 17),
0083     GATE_MM1(CLK_MM_HDMI_PXL, "mm_hdmi_pxl", "rg_fdpi1", 18),
0084     GATE_MM1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll12_div6", 19),
0085     GATE_MM1(CLK_MM_HDMI_ADSP_BCK, "mm_hdmi_adsp_b", "apll12_div4b", 20),
0086     GATE_MM1(CLK_MM_HDMI_PLL, "mm_hdmi_pll", "hdmtx_dig_cts", 21),
0087 };
0088
0089 struct clk_mt8167_mm_driver_data {
0090     const struct mtk_gate *gates_clk;
0091     int gates_num;
0092 };
0093
0094 static const struct clk_mt8167_mm_driver_data mt8167_mmsys_driver_data = {
0095     .gates_clk = mm_clks,
0096     .gates_num = ARRAY_SIZE(mm_clks),
0097 };
0098
0099 static int clk_mt8167_mm_probe(struct platform_device *pdev)
0100 {
0101     struct device *dev = &pdev->dev;
0102     struct device_node *node = dev->parent->of_node;
0103     const struct clk_mt8167_mm_driver_data *data;
0104     struct clk_hw_onecell_data *clk_data;
0105     int ret;
0106
0107     clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
0108     if (!clk_data)
0109         return -ENOMEM;
0110
0111     data = &mt8167_mmsys_driver_data;
0112
0113     ret = mtk_clk_register_gates(node, data->gates_clk, data->gates_num,
0114                      clk_data);
0115     if (ret)
0116         return ret;
0117
0118     ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0119     if (ret)
0120         return ret;
0121
0122     return 0;
0123 }
0124
0125 static struct platform_driver clk_mt8173_mm_drv = {
0126     .driver = {
0127         .name = "clk-mt8167-mm",
0128     },
0129     .probe = clk_mt8167_mm_probe,
0130 };
0131
0132 builtin_platform_driver(clk_mt8173_mm_drv);