clk/mediatek/clk-mt8167-mfgcfg.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2020 MediaTek Inc.
0004  * Copyright (c) 2020 BayLibre, SAS
0005  * Author: James Liao <jamesjj.liao@mediatek.com>
0006  *         Fabien Parent <fparent@baylibre.com>
0007  */
0008
0009 #include <linux/clk-provider.h>
0010 #include <linux/of.h>
0011 #include <linux/of_address.h>
0012 #include <linux/of_device.h>
0013 #include <linux/platform_device.h>
0014
0015 #include "clk-mtk.h"
0016 #include "clk-gate.h"
0017
0018 #include <dt-bindings/clock/mt8167-clk.h>
0019
0020 static const struct mtk_gate_regs mfg_cg_regs = {
0021     .set_ofs = 0x4,
0022     .clr_ofs = 0x8,
0023     .sta_ofs = 0x0,
0024 };
0025
0026 #define GATE_MFG(_id, _name, _parent, _shift) {     \
0027         .id = _id,              \
0028         .name = _name,              \
0029         .parent_name = _parent,         \
0030         .regs = &mfg_cg_regs,           \
0031         .shift = _shift,            \
0032         .ops = &mtk_clk_gate_ops_setclr,    \
0033     }
0034
0035 static const struct mtk_gate mfg_clks[] __initconst = {
0036     GATE_MFG(CLK_MFG_BAXI, "mfg_baxi", "ahb_infra_sel", 0),
0037     GATE_MFG(CLK_MFG_BMEM, "mfg_bmem", "gfmux_emi1x_sel", 1),
0038     GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_mm", 2),
0039     GATE_MFG(CLK_MFG_B26M, "mfg_b26m", "clk26m_ck", 3),
0040 };
0041
0042 static void __init mtk_mfgcfg_init(struct device_node *node)
0043 {
0044     struct clk_hw_onecell_data *clk_data;
0045     int r;
0046
0047     clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK);
0048
0049     mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks), clk_data);
0050
0051     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0052
0053     if (r)
0054         pr_err("%s(): could not register clock provider: %d\n",
0055             __func__, r);
0056
0057 }
0058 CLK_OF_DECLARE(mtk_mfgcfg, "mediatek,mt8167-mfgcfg", mtk_mfgcfg_init);