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0009 #include <linux/clk-provider.h>
0010 #include <linux/of.h>
0011 #include <linux/of_address.h>
0012 #include <linux/of_device.h>
0013 #include <linux/platform_device.h>
0014
0015 #include "clk-mtk.h"
0016 #include "clk-gate.h"
0017
0018 #include <dt-bindings/clock/mt8167-clk.h>
0019
0020 static const struct mtk_gate_regs img_cg_regs = {
0021 .set_ofs = 0x4,
0022 .clr_ofs = 0x8,
0023 .sta_ofs = 0x0,
0024 };
0025
0026 #define GATE_IMG(_id, _name, _parent, _shift) { \
0027 .id = _id, \
0028 .name = _name, \
0029 .parent_name = _parent, \
0030 .regs = &img_cg_regs, \
0031 .shift = _shift, \
0032 .ops = &mtk_clk_gate_ops_setclr, \
0033 }
0034
0035 static const struct mtk_gate img_clks[] __initconst = {
0036 GATE_IMG(CLK_IMG_LARB1_SMI, "img_larb1_smi", "smi_mm", 0),
0037 GATE_IMG(CLK_IMG_CAM_SMI, "img_cam_smi", "smi_mm", 5),
0038 GATE_IMG(CLK_IMG_CAM_CAM, "img_cam_cam", "smi_mm", 6),
0039 GATE_IMG(CLK_IMG_SEN_TG, "img_sen_tg", "cam_mm", 7),
0040 GATE_IMG(CLK_IMG_SEN_CAM, "img_sen_cam", "smi_mm", 8),
0041 GATE_IMG(CLK_IMG_VENC, "img_venc", "smi_mm", 9),
0042 };
0043
0044 static void __init mtk_imgsys_init(struct device_node *node)
0045 {
0046 struct clk_hw_onecell_data *clk_data;
0047 int r;
0048
0049 clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
0050
0051 mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks), clk_data);
0052
0053 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0054
0055 if (r)
0056 pr_err("%s(): could not register clock provider: %d\n",
0057 __func__, r);
0058
0059 }
0060 CLK_OF_DECLARE(mtk_imgsys, "mediatek,mt8167-imgsys", mtk_imgsys_init);