clk/mediatek/clk-mt8167-aud.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2020 MediaTek Inc.
0004  * Copyright (c) 2020 BayLibre, SAS
0005  * Author: James Liao <jamesjj.liao@mediatek.com>
0006  *         Fabien Parent <fparent@baylibre.com>
0007  */
0008
0009 #include <linux/clk-provider.h>
0010 #include <linux/of.h>
0011 #include <linux/of_address.h>
0012 #include <linux/of_device.h>
0013 #include <linux/platform_device.h>
0014
0015 #include "clk-mtk.h"
0016 #include "clk-gate.h"
0017
0018 #include <dt-bindings/clock/mt8167-clk.h>
0019
0020 static const struct mtk_gate_regs aud_cg_regs = {
0021     .set_ofs = 0x0,
0022     .clr_ofs = 0x0,
0023     .sta_ofs = 0x0,
0024 };
0025
0026 #define GATE_AUD(_id, _name, _parent, _shift) { \
0027         .id = _id,          \
0028         .name = _name,          \
0029         .parent_name = _parent,     \
0030         .regs = &aud_cg_regs,       \
0031         .shift = _shift,        \
0032         .ops = &mtk_clk_gate_ops_no_setclr,     \
0033     }
0034
0035 static const struct mtk_gate aud_clks[] __initconst = {
0036     GATE_AUD(CLK_AUD_AFE, "aud_afe", "clk26m_ck", 2),
0037     GATE_AUD(CLK_AUD_I2S, "aud_i2s", "i2s_infra_bck", 6),
0038     GATE_AUD(CLK_AUD_22M, "aud_22m", "rg_aud_engen1", 8),
0039     GATE_AUD(CLK_AUD_24M, "aud_24m", "rg_aud_engen2", 9),
0040     GATE_AUD(CLK_AUD_INTDIR, "aud_intdir", "rg_aud_spdif_in", 15),
0041     GATE_AUD(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "rg_aud_engen2", 18),
0042     GATE_AUD(CLK_AUD_APLL_TUNER, "aud_apll_tuner", "rg_aud_engen1", 19),
0043     GATE_AUD(CLK_AUD_HDMI, "aud_hdmi", "apll12_div4", 20),
0044     GATE_AUD(CLK_AUD_SPDF, "aud_spdf", "apll12_div6", 21),
0045     GATE_AUD(CLK_AUD_ADC, "aud_adc", "aud_afe", 24),
0046     GATE_AUD(CLK_AUD_DAC, "aud_dac", "aud_afe", 25),
0047     GATE_AUD(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "aud_afe", 26),
0048     GATE_AUD(CLK_AUD_TML, "aud_tml", "aud_afe", 27),
0049 };
0050
0051 static void __init mtk_audsys_init(struct device_node *node)
0052 {
0053     struct clk_hw_onecell_data *clk_data;
0054     int r;
0055
0056     clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);
0057
0058     mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), clk_data);
0059
0060     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0061     if (r)
0062         pr_err("%s(): could not register clock provider: %d\n",
0063             __func__, r);
0064
0065 }
0066 CLK_OF_DECLARE(mtk_audsys, "mediatek,mt8167-audsys", mtk_audsys_init);