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0007 #include <linux/clk.h>
0008 #include <linux/of.h>
0009 #include <linux/of_address.h>
0010 #include <linux/slab.h>
0011 #include <linux/mfd/syscon.h>
0012 #include <dt-bindings/clock/mt8135-clk.h>
0013
0014 #include "clk-gate.h"
0015 #include "clk-mtk.h"
0016 #include "clk-pll.h"
0017
0018 static DEFINE_SPINLOCK(mt8135_clk_lock);
0019
0020 static const struct mtk_fixed_factor root_clk_alias[] __initconst = {
0021 FACTOR(CLK_TOP_DSI0_LNTC_DSICLK, "dsi0_lntc_dsiclk", "clk_null", 1, 1),
0022 FACTOR(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_clkdig_cts", "clk_null", 1, 1),
0023 FACTOR(CLK_TOP_CLKPH_MCK, "clkph_mck", "clk_null", 1, 1),
0024 FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "clk_null", 1, 1),
0025 };
0026
0027 static const struct mtk_fixed_factor top_divs[] __initconst = {
0028 FACTOR(CLK_TOP_MAINPLL_806M, "mainpll_806m", "mainpll", 1, 2),
0029 FACTOR(CLK_TOP_MAINPLL_537P3M, "mainpll_537p3m", "mainpll", 1, 3),
0030 FACTOR(CLK_TOP_MAINPLL_322P4M, "mainpll_322p4m", "mainpll", 1, 5),
0031 FACTOR(CLK_TOP_MAINPLL_230P3M, "mainpll_230p3m", "mainpll", 1, 7),
0032
0033 FACTOR(CLK_TOP_UNIVPLL_624M, "univpll_624m", "univpll", 1, 2),
0034 FACTOR(CLK_TOP_UNIVPLL_416M, "univpll_416m", "univpll", 1, 3),
0035 FACTOR(CLK_TOP_UNIVPLL_249P6M, "univpll_249p6m", "univpll", 1, 5),
0036 FACTOR(CLK_TOP_UNIVPLL_178P3M, "univpll_178p3m", "univpll", 1, 7),
0037 FACTOR(CLK_TOP_UNIVPLL_48M, "univpll_48m", "univpll", 1, 26),
0038
0039 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
0040 FACTOR(CLK_TOP_MMPLL_D3, "mmpll_d3", "mmpll", 1, 3),
0041 FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
0042 FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
0043 FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll_d2", 1, 2),
0044 FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll_d3", 1, 2),
0045
0046 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll_806m", 1, 1),
0047 FACTOR(CLK_TOP_SYSPLL_D4, "syspll_d4", "mainpll_806m", 1, 2),
0048 FACTOR(CLK_TOP_SYSPLL_D6, "syspll_d6", "mainpll_806m", 1, 3),
0049 FACTOR(CLK_TOP_SYSPLL_D8, "syspll_d8", "mainpll_806m", 1, 4),
0050 FACTOR(CLK_TOP_SYSPLL_D10, "syspll_d10", "mainpll_806m", 1, 5),
0051 FACTOR(CLK_TOP_SYSPLL_D12, "syspll_d12", "mainpll_806m", 1, 6),
0052 FACTOR(CLK_TOP_SYSPLL_D16, "syspll_d16", "mainpll_806m", 1, 8),
0053 FACTOR(CLK_TOP_SYSPLL_D24, "syspll_d24", "mainpll_806m", 1, 12),
0054
0055 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll_537p3m", 1, 1),
0056
0057 FACTOR(CLK_TOP_SYSPLL_D2P5, "syspll_d2p5", "mainpll_322p4m", 2, 1),
0058 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll_322p4m", 1, 1),
0059
0060 FACTOR(CLK_TOP_SYSPLL_D3P5, "syspll_d3p5", "mainpll_230p3m", 2, 1),
0061
0062 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_624m", 1, 2),
0063 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_624m", 1, 4),
0064 FACTOR(CLK_TOP_UNIVPLL1_D6, "univpll1_d6", "univpll_624m", 1, 6),
0065 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_624m", 1, 8),
0066 FACTOR(CLK_TOP_UNIVPLL1_D10, "univpll1_d10", "univpll_624m", 1, 10),
0067
0068 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_416m", 1, 2),
0069 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_416m", 1, 4),
0070 FACTOR(CLK_TOP_UNIVPLL2_D6, "univpll2_d6", "univpll_416m", 1, 6),
0071 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_416m", 1, 8),
0072
0073 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_416m", 1, 1),
0074 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_249p6m", 1, 1),
0075 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_178p3m", 1, 1),
0076 FACTOR(CLK_TOP_UNIVPLL_D10, "univpll_d10", "univpll_249p6m", 1, 2),
0077 FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_48m", 1, 1),
0078
0079 FACTOR(CLK_TOP_APLL, "apll_ck", "audpll", 1, 1),
0080 FACTOR(CLK_TOP_APLL_D4, "apll_d4", "audpll", 1, 4),
0081 FACTOR(CLK_TOP_APLL_D8, "apll_d8", "audpll", 1, 8),
0082 FACTOR(CLK_TOP_APLL_D16, "apll_d16", "audpll", 1, 16),
0083 FACTOR(CLK_TOP_APLL_D24, "apll_d24", "audpll", 1, 24),
0084
0085 FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
0086 FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
0087 FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
0088
0089 FACTOR(CLK_TOP_LVDSTX_CLKDIG_CT, "lvdstx_clkdig_cts", "lvdspll", 1, 1),
0090 FACTOR(CLK_TOP_VPLL_DPIX, "vpll_dpix_ck", "lvdspll", 1, 1),
0091
0092 FACTOR(CLK_TOP_TVHDMI_H, "tvhdmi_h_ck", "tvdpll", 1, 1),
0093
0094 FACTOR(CLK_TOP_HDMITX_CLKDIG_D2, "hdmitx_clkdig_d2", "hdmitx_clkdig_cts", 1, 2),
0095 FACTOR(CLK_TOP_HDMITX_CLKDIG_D3, "hdmitx_clkdig_d3", "hdmitx_clkdig_cts", 1, 3),
0096
0097 FACTOR(CLK_TOP_TVHDMI_D2, "tvhdmi_d2", "tvhdmi_h_ck", 1, 2),
0098 FACTOR(CLK_TOP_TVHDMI_D4, "tvhdmi_d4", "tvhdmi_h_ck", 1, 4),
0099
0100 FACTOR(CLK_TOP_MEMPLL_MCK_D4, "mempll_mck_d4", "clkph_mck", 1, 4),
0101 };
0102
0103 static const char * const axi_parents[] __initconst = {
0104 "clk26m",
0105 "syspll_d3",
0106 "syspll_d4",
0107 "syspll_d6",
0108 "univpll_d5",
0109 "univpll2_d2",
0110 "syspll_d3p5"
0111 };
0112
0113 static const char * const smi_parents[] __initconst = {
0114 "clk26m",
0115 "clkph_mck",
0116 "syspll_d2p5",
0117 "syspll_d3",
0118 "syspll_d8",
0119 "univpll_d5",
0120 "univpll1_d2",
0121 "univpll1_d6",
0122 "mmpll_d3",
0123 "mmpll_d4",
0124 "mmpll_d5",
0125 "mmpll_d6",
0126 "mmpll_d7",
0127 "vdecpll",
0128 "lvdspll"
0129 };
0130
0131 static const char * const mfg_parents[] __initconst = {
0132 "clk26m",
0133 "univpll1_d4",
0134 "syspll_d2",
0135 "syspll_d2p5",
0136 "syspll_d3",
0137 "univpll_d5",
0138 "univpll1_d2",
0139 "mmpll_d2",
0140 "mmpll_d3",
0141 "mmpll_d4",
0142 "mmpll_d5",
0143 "mmpll_d6",
0144 "mmpll_d7"
0145 };
0146
0147 static const char * const irda_parents[] __initconst = {
0148 "clk26m",
0149 "univpll2_d8",
0150 "univpll1_d6"
0151 };
0152
0153 static const char * const cam_parents[] __initconst = {
0154 "clk26m",
0155 "syspll_d3",
0156 "syspll_d3p5",
0157 "syspll_d4",
0158 "univpll_d5",
0159 "univpll2_d2",
0160 "univpll_d7",
0161 "univpll1_d4"
0162 };
0163
0164 static const char * const aud_intbus_parents[] __initconst = {
0165 "clk26m",
0166 "syspll_d6",
0167 "univpll_d10"
0168 };
0169
0170 static const char * const jpg_parents[] __initconst = {
0171 "clk26m",
0172 "syspll_d5",
0173 "syspll_d4",
0174 "syspll_d3",
0175 "univpll_d7",
0176 "univpll2_d2",
0177 "univpll_d5"
0178 };
0179
0180 static const char * const disp_parents[] __initconst = {
0181 "clk26m",
0182 "syspll_d3p5",
0183 "syspll_d3",
0184 "univpll2_d2",
0185 "univpll_d5",
0186 "univpll1_d2",
0187 "lvdspll",
0188 "vdecpll"
0189 };
0190
0191 static const char * const msdc30_parents[] __initconst = {
0192 "clk26m",
0193 "syspll_d6",
0194 "syspll_d5",
0195 "univpll1_d4",
0196 "univpll2_d4",
0197 "msdcpll"
0198 };
0199
0200 static const char * const usb20_parents[] __initconst = {
0201 "clk26m",
0202 "univpll2_d6",
0203 "univpll1_d10"
0204 };
0205
0206 static const char * const venc_parents[] __initconst = {
0207 "clk26m",
0208 "syspll_d3",
0209 "syspll_d8",
0210 "univpll_d5",
0211 "univpll1_d6",
0212 "mmpll_d4",
0213 "mmpll_d5",
0214 "mmpll_d6"
0215 };
0216
0217 static const char * const spi_parents[] __initconst = {
0218 "clk26m",
0219 "syspll_d6",
0220 "syspll_d8",
0221 "syspll_d10",
0222 "univpll1_d6",
0223 "univpll1_d8"
0224 };
0225
0226 static const char * const uart_parents[] __initconst = {
0227 "clk26m",
0228 "univpll2_d8"
0229 };
0230
0231 static const char * const mem_parents[] __initconst = {
0232 "clk26m",
0233 "clkph_mck"
0234 };
0235
0236 static const char * const camtg_parents[] __initconst = {
0237 "clk26m",
0238 "univpll_d26",
0239 "univpll1_d6",
0240 "syspll_d16",
0241 "syspll_d8"
0242 };
0243
0244 static const char * const audio_parents[] __initconst = {
0245 "clk26m",
0246 "syspll_d24"
0247 };
0248
0249 static const char * const fix_parents[] __initconst = {
0250 "rtc32k",
0251 "clk26m",
0252 "univpll_d5",
0253 "univpll_d7",
0254 "univpll1_d2",
0255 "univpll1_d4",
0256 "univpll1_d6",
0257 "univpll1_d8"
0258 };
0259
0260 static const char * const vdec_parents[] __initconst = {
0261 "clk26m",
0262 "vdecpll",
0263 "clkph_mck",
0264 "syspll_d2p5",
0265 "syspll_d3",
0266 "syspll_d3p5",
0267 "syspll_d4",
0268 "syspll_d5",
0269 "syspll_d6",
0270 "syspll_d8",
0271 "univpll1_d2",
0272 "univpll2_d2",
0273 "univpll_d7",
0274 "univpll_d10",
0275 "univpll2_d4",
0276 "lvdspll"
0277 };
0278
0279 static const char * const ddrphycfg_parents[] __initconst = {
0280 "clk26m",
0281 "axi_sel",
0282 "syspll_d12"
0283 };
0284
0285 static const char * const dpilvds_parents[] __initconst = {
0286 "clk26m",
0287 "lvdspll",
0288 "lvdspll_d2",
0289 "lvdspll_d4",
0290 "lvdspll_d8"
0291 };
0292
0293 static const char * const pmicspi_parents[] __initconst = {
0294 "clk26m",
0295 "univpll2_d6",
0296 "syspll_d8",
0297 "syspll_d10",
0298 "univpll1_d10",
0299 "mempll_mck_d4",
0300 "univpll_d26",
0301 "syspll_d24"
0302 };
0303
0304 static const char * const smi_mfg_as_parents[] __initconst = {
0305 "clk26m",
0306 "smi_sel",
0307 "mfg_sel",
0308 "mem_sel"
0309 };
0310
0311 static const char * const gcpu_parents[] __initconst = {
0312 "clk26m",
0313 "syspll_d4",
0314 "univpll_d7",
0315 "syspll_d5",
0316 "syspll_d6"
0317 };
0318
0319 static const char * const dpi1_parents[] __initconst = {
0320 "clk26m",
0321 "tvhdmi_h_ck",
0322 "tvhdmi_d2",
0323 "tvhdmi_d4"
0324 };
0325
0326 static const char * const cci_parents[] __initconst = {
0327 "clk26m",
0328 "mainpll_537p3m",
0329 "univpll_d3",
0330 "syspll_d2p5",
0331 "syspll_d3",
0332 "syspll_d5"
0333 };
0334
0335 static const char * const apll_parents[] __initconst = {
0336 "clk26m",
0337 "apll_ck",
0338 "apll_d4",
0339 "apll_d8",
0340 "apll_d16",
0341 "apll_d24"
0342 };
0343
0344 static const char * const hdmipll_parents[] __initconst = {
0345 "clk26m",
0346 "hdmitx_clkdig_cts",
0347 "hdmitx_clkdig_d2",
0348 "hdmitx_clkdig_d3"
0349 };
0350
0351 static const struct mtk_composite top_muxes[] __initconst = {
0352
0353 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
0354 0x0140, 0, 3, INVALID_MUX_GATE_BIT),
0355 MUX_GATE(CLK_TOP_SMI_SEL, "smi_sel", smi_parents, 0x0140, 8, 4, 15),
0356 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0140, 16, 4, 23),
0357 MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x0140, 24, 2, 31),
0358
0359 MUX_GATE(CLK_TOP_CAM_SEL, "cam_sel", cam_parents, 0x0144, 0, 3, 7),
0360 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
0361 0x0144, 8, 2, 15),
0362 MUX_GATE(CLK_TOP_JPG_SEL, "jpg_sel", jpg_parents, 0x0144, 16, 3, 23),
0363 MUX_GATE(CLK_TOP_DISP_SEL, "disp_sel", disp_parents, 0x0144, 24, 3, 31),
0364
0365 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents, 0x0148, 0, 3, 7),
0366 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents, 0x0148, 8, 3, 15),
0367 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents, 0x0148, 16, 3, 23),
0368 MUX_GATE(CLK_TOP_MSDC30_4_SEL, "msdc30_4_sel", msdc30_parents, 0x0148, 24, 3, 31),
0369
0370 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x014c, 0, 2, 7),
0371
0372 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0150, 8, 3, 15),
0373 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0150, 16, 3, 23),
0374 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0150, 24, 2, 31),
0375
0376 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0158, 0, 2, 7),
0377 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0158, 8, 3, 15),
0378 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x0158, 24, 2, 31),
0379
0380 MUX_GATE(CLK_TOP_FIX_SEL, "fix_sel", fix_parents, 0x015c, 0, 3, 7),
0381 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x015c, 8, 4, 15),
0382 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
0383 0x015c, 16, 2, 23),
0384 MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x015c, 24, 3, 31),
0385
0386 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x0164, 0, 3, 7),
0387 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents, 0x0164, 8, 3, 15),
0388 MUX_GATE(CLK_TOP_SMI_MFG_AS_SEL, "smi_mfg_as_sel", smi_mfg_as_parents,
0389 0x0164, 16, 2, 23),
0390 MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x0164, 24, 3, 31),
0391
0392 MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, 0x0168, 0, 2, 7),
0393 MUX_GATE(CLK_TOP_CCI_SEL, "cci_sel", cci_parents, 0x0168, 8, 3, 15),
0394 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0168, 16, 3, 23),
0395 MUX_GATE(CLK_TOP_HDMIPLL_SEL, "hdmipll_sel", hdmipll_parents, 0x0168, 24, 2, 31),
0396 };
0397
0398 static const struct mtk_gate_regs infra_cg_regs = {
0399 .set_ofs = 0x0040,
0400 .clr_ofs = 0x0044,
0401 .sta_ofs = 0x0048,
0402 };
0403
0404 #define GATE_ICG(_id, _name, _parent, _shift) { \
0405 .id = _id, \
0406 .name = _name, \
0407 .parent_name = _parent, \
0408 .regs = &infra_cg_regs, \
0409 .shift = _shift, \
0410 .ops = &mtk_clk_gate_ops_setclr, \
0411 }
0412
0413 static const struct mtk_gate infra_clks[] __initconst = {
0414 GATE_ICG(CLK_INFRA_PMIC_WRAP, "pmic_wrap_ck", "axi_sel", 23),
0415 GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22),
0416 GATE_ICG(CLK_INFRA_CCIF1_AP_CTRL, "ccif1_ap_ctrl", "axi_sel", 21),
0417 GATE_ICG(CLK_INFRA_CCIF0_AP_CTRL, "ccif0_ap_ctrl", "axi_sel", 20),
0418 GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16),
0419 GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "cpum_tck_in", 15),
0420 GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8),
0421 GATE_ICG(CLK_INFRA_MFGAXI, "mfgaxi_ck", "axi_sel", 7),
0422 GATE_ICG(CLK_INFRA_DEVAPC, "devapc_ck", "axi_sel", 6),
0423 GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "aud_intbus_sel", 5),
0424 GATE_ICG(CLK_INFRA_MFG_BUS, "mfg_bus_ck", "axi_sel", 2),
0425 GATE_ICG(CLK_INFRA_SMI, "smi_ck", "smi_sel", 1),
0426 GATE_ICG(CLK_INFRA_DBGCLK, "dbgclk_ck", "axi_sel", 0),
0427 };
0428
0429 static const struct mtk_gate_regs peri0_cg_regs = {
0430 .set_ofs = 0x0008,
0431 .clr_ofs = 0x0010,
0432 .sta_ofs = 0x0018,
0433 };
0434
0435 static const struct mtk_gate_regs peri1_cg_regs = {
0436 .set_ofs = 0x000c,
0437 .clr_ofs = 0x0014,
0438 .sta_ofs = 0x001c,
0439 };
0440
0441 #define GATE_PERI0(_id, _name, _parent, _shift) { \
0442 .id = _id, \
0443 .name = _name, \
0444 .parent_name = _parent, \
0445 .regs = &peri0_cg_regs, \
0446 .shift = _shift, \
0447 .ops = &mtk_clk_gate_ops_setclr, \
0448 }
0449
0450 #define GATE_PERI1(_id, _name, _parent, _shift) { \
0451 .id = _id, \
0452 .name = _name, \
0453 .parent_name = _parent, \
0454 .regs = &peri1_cg_regs, \
0455 .shift = _shift, \
0456 .ops = &mtk_clk_gate_ops_setclr, \
0457 }
0458
0459 static const struct mtk_gate peri_gates[] __initconst = {
0460
0461 GATE_PERI0(CLK_PERI_I2C5, "i2c5_ck", "axi_sel", 31),
0462 GATE_PERI0(CLK_PERI_I2C4, "i2c4_ck", "axi_sel", 30),
0463 GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "axi_sel", 29),
0464 GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 28),
0465 GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 27),
0466 GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 26),
0467 GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 25),
0468 GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 24),
0469 GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 23),
0470 GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 22),
0471 GATE_PERI0(CLK_PERI_IRDA, "irda_ck", "irda_sel", 21),
0472 GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 20),
0473 GATE_PERI0(CLK_PERI_MD_HIF, "md_hif_ck", "axi_sel", 19),
0474 GATE_PERI0(CLK_PERI_AP_HIF, "ap_hif_ck", "axi_sel", 18),
0475 GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_4_sel", 17),
0476 GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_3_sel", 16),
0477 GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_2_sel", 15),
0478 GATE_PERI0(CLK_PERI_MSDC20_2, "msdc20_2_ck", "msdc30_1_sel", 14),
0479 GATE_PERI0(CLK_PERI_MSDC20_1, "msdc20_1_ck", "msdc30_0_sel", 13),
0480 GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12),
0481 GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
0482 GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
0483 GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
0484 GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8),
0485 GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7),
0486 GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6),
0487 GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5),
0488 GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4),
0489 GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3),
0490 GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2),
0491 GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
0492 GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "axi_sel", 0),
0493
0494 GATE_PERI1(CLK_PERI_USBSLV, "usbslv_ck", "axi_sel", 8),
0495 GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 7),
0496 GATE_PERI1(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 6),
0497 GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "gcpu_sel", 5),
0498 GATE_PERI1(CLK_PERI_FHCTL, "fhctl_ck", "clk26m", 4),
0499 GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi_sel", 3),
0500 GATE_PERI1(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 2),
0501 GATE_PERI1(CLK_PERI_PERI_PWRAP, "peri_pwrap_ck", "axi_sel", 1),
0502 GATE_PERI1(CLK_PERI_I2C6, "i2c6_ck", "axi_sel", 0),
0503 };
0504
0505 static const char * const uart_ck_sel_parents[] __initconst = {
0506 "clk26m",
0507 "uart_sel",
0508 };
0509
0510 static const struct mtk_composite peri_clks[] __initconst = {
0511 MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1),
0512 MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1),
0513 MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1),
0514 MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
0515 };
0516
0517 static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
0518 static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
0519
0520 static const struct mtk_clk_rst_desc clk_rst_desc[] = {
0521
0522 {
0523 .version = MTK_RST_SIMPLE,
0524 .rst_bank_ofs = infrasys_rst_ofs,
0525 .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
0526 },
0527
0528 {
0529 .version = MTK_RST_SIMPLE,
0530 .rst_bank_ofs = pericfg_rst_ofs,
0531 .rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
0532 }
0533 };
0534
0535 static void __init mtk_topckgen_init(struct device_node *node)
0536 {
0537 struct clk_hw_onecell_data *clk_data;
0538 void __iomem *base;
0539 int r;
0540
0541 base = of_iomap(node, 0);
0542 if (!base) {
0543 pr_err("%s(): ioremap failed\n", __func__);
0544 return;
0545 }
0546
0547 clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
0548
0549 mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_data);
0550 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
0551 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
0552 &mt8135_clk_lock, clk_data);
0553
0554 clk_prepare_enable(clk_data->hws[CLK_TOP_CCI_SEL]->clk);
0555
0556 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0557 if (r)
0558 pr_err("%s(): could not register clock provider: %d\n",
0559 __func__, r);
0560 }
0561 CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8135-topckgen", mtk_topckgen_init);
0562
0563 static void __init mtk_infrasys_init(struct device_node *node)
0564 {
0565 struct clk_hw_onecell_data *clk_data;
0566 int r;
0567
0568 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
0569
0570 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
0571 clk_data);
0572
0573 clk_prepare_enable(clk_data->hws[CLK_INFRA_M4U]->clk);
0574
0575 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0576 if (r)
0577 pr_err("%s(): could not register clock provider: %d\n",
0578 __func__, r);
0579
0580 mtk_register_reset_controller(node, &clk_rst_desc[0]);
0581 }
0582 CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init);
0583
0584 static void __init mtk_pericfg_init(struct device_node *node)
0585 {
0586 struct clk_hw_onecell_data *clk_data;
0587 int r;
0588 void __iomem *base;
0589
0590 base = of_iomap(node, 0);
0591 if (!base) {
0592 pr_err("%s(): ioremap failed\n", __func__);
0593 return;
0594 }
0595
0596 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
0597
0598 mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates),
0599 clk_data);
0600 mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base,
0601 &mt8135_clk_lock, clk_data);
0602
0603 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0604 if (r)
0605 pr_err("%s(): could not register clock provider: %d\n",
0606 __func__, r);
0607
0608 mtk_register_reset_controller(node, &clk_rst_desc[1]);
0609 }
0610 CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init);
0611
0612 #define MT8135_PLL_FMAX (2000 * MHZ)
0613 #define CON0_MT8135_RST_BAR BIT(27)
0614
0615 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \
0616 .id = _id, \
0617 .name = _name, \
0618 .reg = _reg, \
0619 .pwr_reg = _pwr_reg, \
0620 .en_mask = _en_mask, \
0621 .flags = _flags, \
0622 .rst_bar_mask = CON0_MT8135_RST_BAR, \
0623 .fmax = MT8135_PLL_FMAX, \
0624 .pcwbits = _pcwbits, \
0625 .pd_reg = _pd_reg, \
0626 .pd_shift = _pd_shift, \
0627 .tuner_reg = _tuner_reg, \
0628 .pcw_reg = _pcw_reg, \
0629 .pcw_shift = _pcw_shift, \
0630 }
0631
0632 static const struct mtk_pll_data plls[] = {
0633 PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000000, 0, 21, 0x204, 24, 0x0, 0x204, 0),
0634 PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000000, 0, 21, 0x2d0, 24, 0x0, 0x2d0, 0),
0635 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000000, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x220, 0),
0636 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000000, HAVE_RST_BAR, 7, 0x238, 6, 0x0, 0x238, 9),
0637 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000000, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, 0),
0638 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000000, 0, 21, 0x278, 6, 0x0, 0x27c, 0),
0639 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000000, 0, 31, 0x294, 6, 0x0, 0x298, 0),
0640 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0),
0641 PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000000, 0, 31, 0x2e8, 6, 0x2f8, 0x2ec, 0),
0642 PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x304, 0x31c, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x308, 0),
0643 };
0644
0645 static void __init mtk_apmixedsys_init(struct device_node *node)
0646 {
0647 struct clk_hw_onecell_data *clk_data;
0648
0649 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
0650 if (!clk_data)
0651 return;
0652
0653 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
0654 }
0655 CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8135-apmixedsys",
0656 mtk_apmixedsys_init);
