clk/mediatek/clk-mt7986-topckgen.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2021 MediaTek Inc.
0004  * Author: Sam Shih <sam.shih@mediatek.com>
0005  * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
0006  */
0007
0008 #include <linux/clk-provider.h>
0009 #include <linux/of.h>
0010 #include <linux/of_address.h>
0011 #include <linux/of_device.h>
0012 #include <linux/platform_device.h>
0013 #include "clk-mtk.h"
0014 #include "clk-gate.h"
0015 #include "clk-mux.h"
0016
0017 #include <dt-bindings/clock/mt7986-clk.h>
0018 #include <linux/clk.h>
0019
0020 static DEFINE_SPINLOCK(mt7986_clk_lock);
0021
0022 static const struct mtk_fixed_clk top_fixed_clks[] = {
0023     FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000),
0024     FIXED_CLK(CLK_TOP_JTAG, "top_jtag", "clkxtal", 50000000),
0025 };
0026
0027 static const struct mtk_fixed_factor top_divs[] = {
0028     /* XTAL */
0029     FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2),
0030     FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250),
0031     FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220),
0032     /* MPLL */
0033     FACTOR(CLK_TOP_MPLL_D2, "top_mpll_d2", "mpll", 1, 2),
0034     FACTOR(CLK_TOP_MPLL_D4, "top_mpll_d4", "mpll", 1, 4),
0035     FACTOR(CLK_TOP_MPLL_D8, "top_mpll_d8", "mpll", 1, 8),
0036     FACTOR(CLK_TOP_MPLL_D8_D2, "top_mpll_d8_d2", "mpll", 1, 16),
0037     FACTOR(CLK_TOP_MPLL_D3_D2, "top_mpll_d3_d2", "mpll", 1, 6),
0038     /* MMPLL */
0039     FACTOR(CLK_TOP_MMPLL_D2, "top_mmpll_d2", "mmpll", 1, 2),
0040     FACTOR(CLK_TOP_MMPLL_D4, "top_mmpll_d4", "mmpll", 1, 4),
0041     FACTOR(CLK_TOP_MMPLL_D8, "top_mmpll_d8", "mmpll", 1, 8),
0042     FACTOR(CLK_TOP_MMPLL_D8_D2, "top_mmpll_d8_d2", "mmpll", 1, 16),
0043     FACTOR(CLK_TOP_MMPLL_D3_D8, "top_mmpll_d3_d8", "mmpll", 1, 24),
0044     FACTOR(CLK_TOP_MMPLL_U2PHY, "top_mmpll_u2phy", "mmpll", 1, 30),
0045     /* APLL2 */
0046     FACTOR(CLK_TOP_APLL2_D4, "top_apll2_d4", "apll2", 1, 4),
0047     /* NET1PLL */
0048     FACTOR(CLK_TOP_NET1PLL_D4, "top_net1pll_d4", "net1pll", 1, 4),
0049     FACTOR(CLK_TOP_NET1PLL_D5, "top_net1pll_d5", "net1pll", 1, 5),
0050     FACTOR(CLK_TOP_NET1PLL_D5_D2, "top_net1pll_d5_d2", "net1pll", 1, 10),
0051     FACTOR(CLK_TOP_NET1PLL_D5_D4, "top_net1pll_d5_d4", "net1pll", 1, 20),
0052     FACTOR(CLK_TOP_NET1PLL_D8_D2, "top_net1pll_d8_d2", "net1pll", 1, 16),
0053     FACTOR(CLK_TOP_NET1PLL_D8_D4, "top_net1pll_d8_d4", "net1pll", 1, 32),
0054     /* NET2PLL */
0055     FACTOR(CLK_TOP_NET2PLL_D4, "top_net2pll_d4", "net2pll", 1, 4),
0056     FACTOR(CLK_TOP_NET2PLL_D4_D2, "top_net2pll_d4_d2", "net2pll", 1, 8),
0057     FACTOR(CLK_TOP_NET2PLL_D3_D2, "top_net2pll_d3_d2", "net2pll", 1, 2),
0058     /* WEDMCUPLL */
0059     FACTOR(CLK_TOP_WEDMCUPLL_D5_D2, "top_wedmcupll_d5_d2", "wedmcupll", 1,
0060            10),
0061 };
0062
0063 static const char *const nfi1x_parents[] __initconst = { "top_xtal",
0064                              "top_mmpll_d8",
0065                              "top_net1pll_d8_d2",
0066                              "top_net2pll_d3_d2",
0067                              "top_mpll_d4",
0068                              "top_mmpll_d8_d2",
0069                              "top_wedmcupll_d5_d2",
0070                              "top_mpll_d8" };
0071
0072 static const char *const spinfi_parents[] __initconst = {
0073     "top_xtal_d2",     "top_xtal",  "top_net1pll_d5_d4",
0074     "top_mpll_d4",     "top_mmpll_d8_d2", "top_wedmcupll_d5_d2",
0075     "top_mmpll_d3_d8", "top_mpll_d8"
0076 };
0077
0078 static const char *const spi_parents[] __initconst = {
0079     "top_xtal",   "top_mpll_d2",    "top_mmpll_d8",
0080     "top_net1pll_d8_d2", "top_net2pll_d3_d2",  "top_net1pll_d5_d4",
0081     "top_mpll_d4",       "top_wedmcupll_d5_d2"
0082 };
0083
0084 static const char *const uart_parents[] __initconst = { "top_xtal",
0085                             "top_mpll_d8",
0086                             "top_mpll_d8_d2" };
0087
0088 static const char *const pwm_parents[] __initconst = {
0089     "top_xtal", "top_net1pll_d8_d2", "top_net1pll_d5_d4", "top_mpll_d4"
0090 };
0091
0092 static const char *const i2c_parents[] __initconst = {
0093     "top_xtal", "top_net1pll_d5_d4", "top_mpll_d4", "top_net1pll_d8_d4"
0094 };
0095
0096 static const char *const pextp_tl_ck_parents[] __initconst = {
0097     "top_xtal", "top_net1pll_d5_d4", "top_net2pll_d4_d2", "top_rtc_32k"
0098 };
0099
0100 static const char *const emmc_250m_parents[] __initconst = {
0101     "top_xtal", "top_net1pll_d5_d2"
0102 };
0103
0104 static const char *const emmc_416m_parents[] __initconst = { "top_xtal",
0105                                  "mpll" };
0106
0107 static const char *const f_26m_adc_parents[] __initconst = { "top_xtal",
0108                                  "top_mpll_d8_d2" };
0109
0110 static const char *const dramc_md32_parents[] __initconst = { "top_xtal",
0111                                   "top_mpll_d2" };
0112
0113 static const char *const sysaxi_parents[] __initconst = { "top_xtal",
0114                               "top_net1pll_d8_d2",
0115                               "top_net2pll_d4" };
0116
0117 static const char *const sysapb_parents[] __initconst = { "top_xtal",
0118                               "top_mpll_d3_d2",
0119                               "top_net2pll_d4_d2" };
0120
0121 static const char *const arm_db_main_parents[] __initconst = {
0122     "top_xtal", "top_net2pll_d3_d2"
0123 };
0124
0125 static const char *const arm_db_jtsel_parents[] __initconst = { "top_jtag",
0126                                 "top_xtal" };
0127
0128 static const char *const netsys_parents[] __initconst = { "top_xtal",
0129                               "top_mmpll_d4" };
0130
0131 static const char *const netsys_500m_parents[] __initconst = {
0132     "top_xtal", "top_net1pll_d5"
0133 };
0134
0135 static const char *const netsys_mcu_parents[] __initconst = {
0136     "top_xtal", "wedmcupll", "top_mmpll_d2", "top_net1pll_d4",
0137     "top_net1pll_d5"
0138 };
0139
0140 static const char *const netsys_2x_parents[] __initconst = {
0141     "top_xtal", "net2pll", "wedmcupll", "top_mmpll_d2"
0142 };
0143
0144 static const char *const sgm_325m_parents[] __initconst = { "top_xtal",
0145                                 "sgmpll" };
0146
0147 static const char *const sgm_reg_parents[] __initconst = {
0148     "top_xtal", "top_net1pll_d8_d4"
0149 };
0150
0151 static const char *const a1sys_parents[] __initconst = { "top_xtal",
0152                              "top_apll2_d4" };
0153
0154 static const char *const conn_mcusys_parents[] __initconst = { "top_xtal",
0155                                    "top_mmpll_d2" };
0156
0157 static const char *const eip_b_parents[] __initconst = { "top_xtal",
0158                              "net2pll" };
0159
0160 static const char *const aud_l_parents[] __initconst = { "top_xtal", "apll2",
0161                              "top_mpll_d8_d2" };
0162
0163 static const char *const a_tuner_parents[] __initconst = { "top_xtal",
0164                                "top_apll2_d4",
0165                                "top_mpll_d8_d2" };
0166
0167 static const char *const u2u3_sys_parents[] __initconst = {
0168     "top_xtal", "top_net1pll_d5_d4"
0169 };
0170
0171 static const char *const da_u2_refsel_parents[] __initconst = {
0172     "top_xtal", "top_mmpll_u2phy"
0173 };
0174
0175 static const struct mtk_mux top_muxes[] = {
0176     /* CLK_CFG_0 */
0177     MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
0178                  0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
0179     MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
0180                  0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
0181     MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000,
0182                  0x004, 0x008, 16, 3, 23, 0x1C0, 2),
0183     MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
0184                  0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
0185     /* CLK_CFG_1 */
0186     MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010,
0187                  0x014, 0x018, 0, 2, 7, 0x1C0, 4),
0188     MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010,
0189                  0x014, 0x018, 8, 2, 15, 0x1C0, 5),
0190     MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010,
0191                  0x014, 0x018, 16, 2, 23, 0x1C0, 6),
0192     MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
0193                  pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2,
0194                  31, 0x1C0, 7),
0195     /* CLK_CFG_2 */
0196     MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel",
0197                  emmc_250m_parents, 0x020, 0x024, 0x028, 0, 1, 7,
0198                  0x1C0, 8),
0199     MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_416M_SEL, "emmc_416m_sel",
0200                  emmc_416m_parents, 0x020, 0x024, 0x028, 8, 1, 15,
0201                  0x1C0, 9),
0202     MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel",
0203                  f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23,
0204                  0x1C0, 10),
0205     MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents,
0206                  0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11),
0207     /* CLK_CFG_3 */
0208     MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
0209                  dramc_md32_parents, 0x030, 0x034, 0x038, 0, 1, 7,
0210                  0x1C0, 12),
0211     MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents,
0212                  0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13),
0213     MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents,
0214                  0x030, 0x034, 0x038, 16, 2, 23, 0x1C0, 14),
0215     MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
0216                  arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1,
0217                  31, 0x1C0, 15),
0218     /* CLK_CFG_4 */
0219     MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_JTSEL, "arm_db_jtsel",
0220                  arm_db_jtsel_parents, 0x040, 0x044, 0x048, 0, 1, 7,
0221                  0x1C0, 16),
0222     MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
0223                  0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17),
0224     MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
0225                  netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1,
0226                  23, 0x1C0, 18),
0227     MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
0228                  netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31,
0229                  0x1C0, 19),
0230     /* CLK_CFG_5 */
0231     MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
0232                  netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7,
0233                  0x1C0, 20),
0234     MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
0235                  sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
0236                  0x1C0, 21),
0237     MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel",
0238                  sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23,
0239                  0x1C0, 22),
0240     MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
0241                  0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23),
0242     /* CLK_CFG_6 */
0243     MUX_GATE_CLR_SET_UPD(CLK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel",
0244                  conn_mcusys_parents, 0x060, 0x064, 0x068, 0, 1, 7,
0245                  0x1C0, 24),
0246     MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents,
0247                  0x060, 0x064, 0x068, 8, 1, 15, 0x1C0, 25),
0248     MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_PHY_SEL, "pcie_phy_sel",
0249                  f_26m_adc_parents, 0x060, 0x064, 0x068, 16, 1, 23,
0250                  0x1C0, 26),
0251     MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel",
0252                  f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31,
0253                  0x1C0, 27),
0254     /* CLK_CFG_7 */
0255     MUX_GATE_CLR_SET_UPD(CLK_TOP_F26M_SEL, "csw_f26m_sel",
0256                  f_26m_adc_parents, 0x070, 0x074, 0x078, 0, 1, 7,
0257                  0x1C0, 28),
0258     MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
0259                  0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29),
0260     MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel",
0261                  a_tuner_parents, 0x070, 0x074, 0x078, 16, 2, 23,
0262                  0x1C0, 30),
0263     MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents,
0264                  0x070, 0x074, 0x078, 24, 1, 31, 0x1C4, 0),
0265     /* CLK_CFG_8 */
0266     MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel",
0267                  u2u3_sys_parents, 0x080, 0x084, 0x088, 0, 1, 7,
0268                  0x1C4, 1),
0269     MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel",
0270                  u2u3_sys_parents, 0x080, 0x084, 0x088, 8, 1, 15,
0271                  0x1C4, 2),
0272     MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_REFSEL, "da_u2_refsel",
0273                  da_u2_refsel_parents, 0x080, 0x084, 0x088, 16, 1,
0274                  23, 0x1C4, 3),
0275     MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel",
0276                  da_u2_refsel_parents, 0x080, 0x084, 0x088, 24, 1,
0277                  31, 0x1C4, 4),
0278     /* CLK_CFG_9 */
0279     MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel",
0280                  sgm_reg_parents, 0x090, 0x094, 0x098, 0, 1, 7,
0281                  0x1C4, 5),
0282 };
0283
0284 static int clk_mt7986_topckgen_probe(struct platform_device *pdev)
0285 {
0286     struct clk_hw_onecell_data *clk_data;
0287     struct device_node *node = pdev->dev.of_node;
0288     int r;
0289     void __iomem *base;
0290     int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) +
0291          ARRAY_SIZE(top_muxes);
0292
0293     base = of_iomap(node, 0);
0294     if (!base) {
0295         pr_err("%s(): ioremap failed\n", __func__);
0296         return -ENOMEM;
0297     }
0298
0299     clk_data = mtk_alloc_clk_data(nr);
0300     if (!clk_data)
0301         return -ENOMEM;
0302
0303     mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
0304                     clk_data);
0305     mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
0306     mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
0307                    &mt7986_clk_lock, clk_data);
0308
0309     clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAXI_SEL]->clk);
0310     clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAPB_SEL]->clk);
0311     clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_SEL]->clk);
0312     clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_MD32_SEL]->clk);
0313     clk_prepare_enable(clk_data->hws[CLK_TOP_F26M_SEL]->clk);
0314     clk_prepare_enable(clk_data->hws[CLK_TOP_SGM_REG_SEL]->clk);
0315
0316     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0317
0318     if (r) {
0319         pr_err("%s(): could not register clock provider: %d\n",
0320                __func__, r);
0321         goto free_topckgen_data;
0322     }
0323     return r;
0324
0325 free_topckgen_data:
0326     mtk_free_clk_data(clk_data);
0327     return r;
0328 }
0329
0330 static const struct of_device_id of_match_clk_mt7986_topckgen[] = {
0331     { .compatible = "mediatek,mt7986-topckgen", },
0332     {}
0333 };
0334
0335 static struct platform_driver clk_mt7986_topckgen_drv = {
0336     .probe = clk_mt7986_topckgen_probe,
0337     .driver = {
0338         .name = "clk-mt7986-topckgen",
0339         .of_match_table = of_match_clk_mt7986_topckgen,
0340     },
0341 };
0342 builtin_platform_driver(clk_mt7986_topckgen_drv);