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0008 #include <linux/clk-provider.h>
0009 #include <linux/of.h>
0010 #include <linux/of_address.h>
0011 #include <linux/of_device.h>
0012 #include <linux/platform_device.h>
0013 #include "clk-mtk.h"
0014 #include "clk-gate.h"
0015 #include "clk-mux.h"
0016
0017 #include <dt-bindings/clock/mt7986-clk.h>
0018 #include <linux/clk.h>
0019
0020 static DEFINE_SPINLOCK(mt7986_clk_lock);
0021
0022 static const struct mtk_fixed_factor infra_divs[] = {
0023 FACTOR(CLK_INFRA_SYSAXI_D2, "infra_sysaxi_d2", "sysaxi_sel", 1, 2),
0024 };
0025
0026 static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel",
0027 "uart_sel" };
0028
0029 static const char *const infra_spi_parents[] __initconst = { "i2c_sel",
0030 "spi_sel" };
0031
0032 static const char *const infra_pwm_bsel_parents[] __initconst = {
0033 "top_rtc_32p7k", "csw_f26m_sel", "infra_sysaxi_d2", "pwm_sel"
0034 };
0035
0036 static const char *const infra_pcie_parents[] __initconst = {
0037 "top_rtc_32p7k", "csw_f26m_sel", "top_xtal", "pextp_tl_ck_sel"
0038 };
0039
0040 static const struct mtk_mux infra_muxes[] = {
0041
0042 MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel",
0043 infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1,
0044 -1, -1, -1),
0045 MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel",
0046 infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1,
0047 -1, -1, -1),
0048 MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel",
0049 infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1,
0050 -1, -1, -1),
0051 MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel",
0052 infra_spi_parents, 0x0018, 0x0010, 0x0014, 4, 1,
0053 -1, -1, -1),
0054 MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel",
0055 infra_spi_parents, 0x0018, 0x0010, 0x0014, 5, 1,
0056 -1, -1, -1),
0057 MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel",
0058 infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 9,
0059 2, -1, -1, -1),
0060 MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel",
0061 infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 11,
0062 2, -1, -1, -1),
0063 MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel",
0064 infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13,
0065 2, -1, -1, -1),
0066
0067 MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel",
0068 infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2,
0069 -1, -1, -1),
0070 };
0071
0072 static const struct mtk_gate_regs infra0_cg_regs = {
0073 .set_ofs = 0x40,
0074 .clr_ofs = 0x44,
0075 .sta_ofs = 0x48,
0076 };
0077
0078 static const struct mtk_gate_regs infra1_cg_regs = {
0079 .set_ofs = 0x50,
0080 .clr_ofs = 0x54,
0081 .sta_ofs = 0x58,
0082 };
0083
0084 static const struct mtk_gate_regs infra2_cg_regs = {
0085 .set_ofs = 0x60,
0086 .clr_ofs = 0x64,
0087 .sta_ofs = 0x68,
0088 };
0089
0090 #define GATE_INFRA0(_id, _name, _parent, _shift) \
0091 { \
0092 .id = _id, .name = _name, .parent_name = _parent, \
0093 .regs = &infra0_cg_regs, .shift = _shift, \
0094 .ops = &mtk_clk_gate_ops_setclr, \
0095 }
0096
0097 #define GATE_INFRA1(_id, _name, _parent, _shift) \
0098 { \
0099 .id = _id, .name = _name, .parent_name = _parent, \
0100 .regs = &infra1_cg_regs, .shift = _shift, \
0101 .ops = &mtk_clk_gate_ops_setclr, \
0102 }
0103
0104 #define GATE_INFRA2(_id, _name, _parent, _shift) \
0105 { \
0106 .id = _id, .name = _name, .parent_name = _parent, \
0107 .regs = &infra2_cg_regs, .shift = _shift, \
0108 .ops = &mtk_clk_gate_ops_setclr, \
0109 }
0110
0111 static const struct mtk_gate infra_clks[] = {
0112
0113 GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_sysaxi_d2", 0),
0114 GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_sysaxi_d2", 1),
0115 GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2),
0116 GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3),
0117 GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4),
0118 GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi_sel", 6),
0119 GATE_INFRA0(CLK_INFRA_EIP97_CK, "infra_eip97", "eip_b_sel", 7),
0120 GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi_sel", 8),
0121 GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9),
0122 GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l_sel", 10),
0123 GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys_sel", 11),
0124 GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner_sel", 13),
0125 GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel",
0126 14),
0127 GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_sysaxi_d2", 15),
0128 GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_sysaxi_d2", 16),
0129 GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_sysaxi_d2", 24),
0130 GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25),
0131 GATE_INFRA0(CLK_INFRA_TRNG_CK, "infra_trng", "sysaxi_sel", 26),
0132
0133 GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0),
0134 GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_sel", 1),
0135 GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2),
0136 GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3),
0137 GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4),
0138 GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x_sel", 8),
0139 GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_sel", 9),
0140 GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_sysaxi_d2",
0141 10),
0142 GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11),
0143 GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12),
0144 GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_sysaxi_d2",
0145 13),
0146 GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_sysaxi_d2",
0147 14),
0148 GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "top_rtc_32k", 15),
0149 GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_416m_sel", 16),
0150 GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_250m_sel",
0151 17),
0152 GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi_sel",
0153 18),
0154 GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "infra_sysaxi_d2",
0155 19),
0156 GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "csw_f26m_sel", 20),
0157 GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m_sel", 21),
0158 GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x_sel", 23),
0159
0160 GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi_sel", 0),
0161 GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "infra_sysaxi_d2",
0162 1),
0163 GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys_sel", 2),
0164 GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_sel", 3),
0165 GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl_ck_sel", 12),
0166 GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "top_xtal",
0167 13),
0168 GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m_sel", 14),
0169 GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi_sel", 15),
0170 };
0171
0172 static int clk_mt7986_infracfg_probe(struct platform_device *pdev)
0173 {
0174 struct clk_hw_onecell_data *clk_data;
0175 struct device_node *node = pdev->dev.of_node;
0176 int r;
0177 void __iomem *base;
0178 int nr = ARRAY_SIZE(infra_divs) + ARRAY_SIZE(infra_muxes) +
0179 ARRAY_SIZE(infra_clks);
0180
0181 base = of_iomap(node, 0);
0182 if (!base) {
0183 pr_err("%s(): ioremap failed\n", __func__);
0184 return -ENOMEM;
0185 }
0186
0187 clk_data = mtk_alloc_clk_data(nr);
0188
0189 if (!clk_data)
0190 return -ENOMEM;
0191
0192 mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
0193 mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
0194 &mt7986_clk_lock, clk_data);
0195 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
0196 clk_data);
0197
0198 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0199 if (r) {
0200 pr_err("%s(): could not register clock provider: %d\n",
0201 __func__, r);
0202 goto free_infracfg_data;
0203 }
0204 return r;
0205
0206 free_infracfg_data:
0207 mtk_free_clk_data(clk_data);
0208 return r;
0209
0210 }
0211
0212 static const struct of_device_id of_match_clk_mt7986_infracfg[] = {
0213 { .compatible = "mediatek,mt7986-infracfg", },
0214 {}
0215 };
0216
0217 static struct platform_driver clk_mt7986_infracfg_drv = {
0218 .probe = clk_mt7986_infracfg_probe,
0219 .driver = {
0220 .name = "clk-mt7986-infracfg",
0221 .of_match_table = of_match_clk_mt7986_infracfg,
0222 },
0223 };
0224 builtin_platform_driver(clk_mt7986_infracfg_drv);
