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0008 #include <linux/clk.h>
0009 #include <linux/clk-provider.h>
0010 #include <linux/of.h>
0011 #include <linux/of_address.h>
0012 #include <linux/of_device.h>
0013 #include <linux/platform_device.h>
0014
0015 #include "clk-cpumux.h"
0016 #include "clk-gate.h"
0017 #include "clk-mtk.h"
0018 #include "clk-pll.h"
0019
0020 #include <dt-bindings/clock/mt7629-clk.h>
0021
0022 #define MT7629_PLL_FMAX (2500UL * MHZ)
0023 #define CON0_MT7629_RST_BAR BIT(24)
0024
0025 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
0026 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
0027 _pcw_shift, _div_table, _parent_name) { \
0028 .id = _id, \
0029 .name = _name, \
0030 .reg = _reg, \
0031 .pwr_reg = _pwr_reg, \
0032 .en_mask = _en_mask, \
0033 .flags = _flags, \
0034 .rst_bar_mask = CON0_MT7629_RST_BAR, \
0035 .fmax = MT7629_PLL_FMAX, \
0036 .pcwbits = _pcwbits, \
0037 .pd_reg = _pd_reg, \
0038 .pd_shift = _pd_shift, \
0039 .tuner_reg = _tuner_reg, \
0040 .pcw_reg = _pcw_reg, \
0041 .pcw_shift = _pcw_shift, \
0042 .div_table = _div_table, \
0043 .parent_name = _parent_name, \
0044 }
0045
0046 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
0047 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
0048 _pcw_shift) \
0049 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
0050 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
0051 NULL, "clk20m")
0052
0053 #define GATE_APMIXED(_id, _name, _parent, _shift) { \
0054 .id = _id, \
0055 .name = _name, \
0056 .parent_name = _parent, \
0057 .regs = &apmixed_cg_regs, \
0058 .shift = _shift, \
0059 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
0060 }
0061
0062 #define GATE_INFRA(_id, _name, _parent, _shift) { \
0063 .id = _id, \
0064 .name = _name, \
0065 .parent_name = _parent, \
0066 .regs = &infra_cg_regs, \
0067 .shift = _shift, \
0068 .ops = &mtk_clk_gate_ops_setclr, \
0069 }
0070
0071 #define GATE_PERI0(_id, _name, _parent, _shift) { \
0072 .id = _id, \
0073 .name = _name, \
0074 .parent_name = _parent, \
0075 .regs = &peri0_cg_regs, \
0076 .shift = _shift, \
0077 .ops = &mtk_clk_gate_ops_setclr, \
0078 }
0079
0080 #define GATE_PERI1(_id, _name, _parent, _shift) { \
0081 .id = _id, \
0082 .name = _name, \
0083 .parent_name = _parent, \
0084 .regs = &peri1_cg_regs, \
0085 .shift = _shift, \
0086 .ops = &mtk_clk_gate_ops_setclr, \
0087 }
0088
0089 static DEFINE_SPINLOCK(mt7629_clk_lock);
0090
0091 static const char * const axi_parents[] = {
0092 "clkxtal",
0093 "syspll1_d2",
0094 "syspll_d5",
0095 "syspll1_d4",
0096 "univpll_d5",
0097 "univpll2_d2",
0098 "univpll_d7",
0099 "dmpll_ck"
0100 };
0101
0102 static const char * const mem_parents[] = {
0103 "clkxtal",
0104 "dmpll_ck"
0105 };
0106
0107 static const char * const ddrphycfg_parents[] = {
0108 "clkxtal",
0109 "syspll1_d8"
0110 };
0111
0112 static const char * const eth_parents[] = {
0113 "clkxtal",
0114 "syspll1_d2",
0115 "univpll1_d2",
0116 "syspll1_d4",
0117 "univpll_d5",
0118 "sgmiipll_d2",
0119 "univpll_d7",
0120 "dmpll_ck"
0121 };
0122
0123 static const char * const pwm_parents[] = {
0124 "clkxtal",
0125 "univpll2_d4"
0126 };
0127
0128 static const char * const f10m_ref_parents[] = {
0129 "clkxtal",
0130 "sgmiipll_d2"
0131 };
0132
0133 static const char * const nfi_infra_parents[] = {
0134 "clkxtal",
0135 "clkxtal",
0136 "clkxtal",
0137 "clkxtal",
0138 "clkxtal",
0139 "clkxtal",
0140 "univpll2_d8",
0141 "univpll3_d4",
0142 "syspll1_d8",
0143 "univpll1_d8",
0144 "syspll4_d2",
0145 "syspll2_d4",
0146 "univpll2_d4",
0147 "univpll3_d2",
0148 "syspll1_d4",
0149 "syspll_d7"
0150 };
0151
0152 static const char * const flash_parents[] = {
0153 "clkxtal",
0154 "univpll_d80_d4",
0155 "syspll2_d8",
0156 "syspll3_d4",
0157 "univpll3_d4",
0158 "univpll1_d8",
0159 "syspll2_d4",
0160 "univpll2_d4"
0161 };
0162
0163 static const char * const uart_parents[] = {
0164 "clkxtal",
0165 "univpll2_d8"
0166 };
0167
0168 static const char * const spi0_parents[] = {
0169 "clkxtal",
0170 "syspll3_d2",
0171 "clkxtal",
0172 "syspll2_d4",
0173 "syspll4_d2",
0174 "univpll2_d4",
0175 "univpll1_d8",
0176 "clkxtal"
0177 };
0178
0179 static const char * const spi1_parents[] = {
0180 "clkxtal",
0181 "syspll3_d2",
0182 "clkxtal",
0183 "syspll4_d4",
0184 "syspll4_d2",
0185 "univpll2_d4",
0186 "univpll1_d8",
0187 "clkxtal"
0188 };
0189
0190 static const char * const msdc30_0_parents[] = {
0191 "clkxtal",
0192 "univpll2_d16",
0193 "univ48m"
0194 };
0195
0196 static const char * const msdc30_1_parents[] = {
0197 "clkxtal",
0198 "univpll2_d16",
0199 "univ48m",
0200 "syspll2_d4",
0201 "univpll2_d4",
0202 "syspll_d7",
0203 "syspll2_d2",
0204 "univpll2_d2"
0205 };
0206
0207 static const char * const ap2wbmcu_parents[] = {
0208 "clkxtal",
0209 "syspll1_d2",
0210 "univ48m",
0211 "syspll1_d8",
0212 "univpll2_d4",
0213 "syspll_d7",
0214 "syspll2_d2",
0215 "univpll2_d2"
0216 };
0217
0218 static const char * const audio_parents[] = {
0219 "clkxtal",
0220 "syspll3_d4",
0221 "syspll4_d4",
0222 "syspll1_d16"
0223 };
0224
0225 static const char * const aud_intbus_parents[] = {
0226 "clkxtal",
0227 "syspll1_d4",
0228 "syspll4_d2",
0229 "dmpll_d4"
0230 };
0231
0232 static const char * const pmicspi_parents[] = {
0233 "clkxtal",
0234 "syspll1_d8",
0235 "syspll3_d4",
0236 "syspll1_d16",
0237 "univpll3_d4",
0238 "clkxtal",
0239 "univpll2_d4",
0240 "dmpll_d8"
0241 };
0242
0243 static const char * const scp_parents[] = {
0244 "clkxtal",
0245 "syspll1_d8",
0246 "univpll2_d2",
0247 "univpll2_d4"
0248 };
0249
0250 static const char * const atb_parents[] = {
0251 "clkxtal",
0252 "syspll1_d2",
0253 "syspll_d5"
0254 };
0255
0256 static const char * const hif_parents[] = {
0257 "clkxtal",
0258 "syspll1_d2",
0259 "univpll1_d2",
0260 "syspll1_d4",
0261 "univpll_d5",
0262 "clk_null",
0263 "univpll_d7"
0264 };
0265
0266 static const char * const sata_parents[] = {
0267 "clkxtal",
0268 "univpll2_d4"
0269 };
0270
0271 static const char * const usb20_parents[] = {
0272 "clkxtal",
0273 "univpll3_d4",
0274 "syspll1_d8"
0275 };
0276
0277 static const char * const aud1_parents[] = {
0278 "clkxtal"
0279 };
0280
0281 static const char * const irrx_parents[] = {
0282 "clkxtal",
0283 "syspll4_d16"
0284 };
0285
0286 static const char * const crypto_parents[] = {
0287 "clkxtal",
0288 "univpll_d3",
0289 "univpll1_d2",
0290 "syspll1_d2",
0291 "univpll_d5",
0292 "syspll_d5",
0293 "univpll2_d2",
0294 "syspll_d2"
0295 };
0296
0297 static const char * const gpt10m_parents[] = {
0298 "clkxtal",
0299 "clkxtal_d4"
0300 };
0301
0302 static const char * const peribus_ck_parents[] = {
0303 "syspll1_d8",
0304 "syspll1_d4"
0305 };
0306
0307 static const char * const infra_mux1_parents[] = {
0308 "clkxtal",
0309 "armpll",
0310 "main_core_en",
0311 "armpll"
0312 };
0313
0314 static const struct mtk_gate_regs apmixed_cg_regs = {
0315 .set_ofs = 0x8,
0316 .clr_ofs = 0x8,
0317 .sta_ofs = 0x8,
0318 };
0319
0320 static const struct mtk_gate_regs infra_cg_regs = {
0321 .set_ofs = 0x40,
0322 .clr_ofs = 0x44,
0323 .sta_ofs = 0x48,
0324 };
0325
0326 static const struct mtk_gate_regs peri0_cg_regs = {
0327 .set_ofs = 0x8,
0328 .clr_ofs = 0x10,
0329 .sta_ofs = 0x18,
0330 };
0331
0332 static const struct mtk_gate_regs peri1_cg_regs = {
0333 .set_ofs = 0xC,
0334 .clr_ofs = 0x14,
0335 .sta_ofs = 0x1C,
0336 };
0337
0338 static const struct mtk_pll_data plls[] = {
0339 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0,
0340 0, 21, 0x0204, 24, 0, 0x0204, 0),
0341 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0,
0342 HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
0343 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0,
0344 HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
0345 PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0,
0346 0, 21, 0x0300, 1, 0, 0x0304, 0),
0347 PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0,
0348 0, 21, 0x0314, 1, 0, 0x0318, 0),
0349 PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0,
0350 0, 21, 0x0358, 1, 0, 0x035C, 0),
0351 };
0352
0353 static const struct mtk_gate apmixed_clks[] = {
0354 GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5),
0355 };
0356
0357 static const struct mtk_gate infra_clks[] = {
0358 GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "hd_faxi", 0),
0359 GATE_INFRA(CLK_INFRA_TRNG_PD, "infra_trng_pd", "hd_faxi", 2),
0360 GATE_INFRA(CLK_INFRA_DEVAPC_PD, "infra_devapc_pd", "hd_faxi", 4),
0361 GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "infrao_10m", 18),
0362 GATE_INFRA(CLK_INFRA_SEJ_PD, "infra_sej_pd", "infrao_10m", 19),
0363 };
0364
0365 static const struct mtk_fixed_clk top_fixed_clks[] = {
0366 FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal",
0367 31250000),
0368 FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, "to_u2_phy_1p", "clkxtal",
0369 31250000),
0370 FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, "pcie0_pipe_en", "clkxtal",
0371 125000000),
0372 FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, "pcie1_pipe_en", "clkxtal",
0373 125000000),
0374 FIXED_CLK(CLK_TOP_SSUSB_TX250M, "ssusb_tx250m", "clkxtal",
0375 250000000),
0376 FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, "ssusb_eq_rx250m", "clkxtal",
0377 250000000),
0378 FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, "ssusb_cdr_ref", "clkxtal",
0379 33333333),
0380 FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, "ssusb_cdr_fb", "clkxtal",
0381 50000000),
0382 FIXED_CLK(CLK_TOP_SATA_ASIC, "sata_asic", "clkxtal",
0383 50000000),
0384 FIXED_CLK(CLK_TOP_SATA_RBC, "sata_rbc", "clkxtal",
0385 50000000),
0386 };
0387
0388 static const struct mtk_fixed_factor top_divs[] = {
0389 FACTOR(CLK_TOP_TO_USB3_SYS, "to_usb3_sys", "eth1pll", 1, 4),
0390 FACTOR(CLK_TOP_P1_1MHZ, "p1_1mhz", "eth1pll", 1, 500),
0391 FACTOR(CLK_TOP_4MHZ, "free_run_4mhz", "eth1pll", 1, 125),
0392 FACTOR(CLK_TOP_P0_1MHZ, "p0_1mhz", "eth1pll", 1, 500),
0393 FACTOR(CLK_TOP_ETH_500M, "eth_500m", "eth1pll", 1, 1),
0394 FACTOR(CLK_TOP_TXCLK_SRC_PRE, "txclk_src_pre", "sgmiipll_d2", 1, 1),
0395 FACTOR(CLK_TOP_RTC, "rtc", "clkxtal", 1, 1024),
0396 FACTOR(CLK_TOP_PWM_QTR_26M, "pwm_qtr_26m", "clkxtal", 1, 1),
0397 FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "cpum_tck", 1, 1),
0398 FACTOR(CLK_TOP_TO_USB3_DA_TOP, "to_usb3_da_top", "clkxtal", 1, 1),
0399 FACTOR(CLK_TOP_MEMPLL, "mempll", "clkxtal", 32, 1),
0400 FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
0401 FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "mempll", 1, 4),
0402 FACTOR(CLK_TOP_DMPLL_D8, "dmpll_d8", "mempll", 1, 8),
0403 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
0404 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4),
0405 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8),
0406 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16),
0407 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "mainpll", 1, 32),
0408 FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "mainpll", 1, 6),
0409 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12),
0410 FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24),
0411 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
0412 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10),
0413 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20),
0414 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
0415 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
0416 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28),
0417 FACTOR(CLK_TOP_SYSPLL4_D16, "syspll4_d16", "mainpll", 1, 112),
0418 FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2),
0419 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
0420 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8),
0421 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16),
0422 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
0423 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6),
0424 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12),
0425 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24),
0426 FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll", 1, 48),
0427 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
0428 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10),
0429 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20),
0430 FACTOR(CLK_TOP_UNIVPLL3_D16, "univpll3_d16", "univpll", 1, 80),
0431 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
0432 FACTOR(CLK_TOP_UNIVPLL_D80_D4, "univpll_d80_d4", "univpll", 1, 320),
0433 FACTOR(CLK_TOP_UNIV48M, "univ48m", "univpll", 1, 25),
0434 FACTOR(CLK_TOP_SGMIIPLL_D2, "sgmiipll_d2", "sgmipll", 1, 2),
0435 FACTOR(CLK_TOP_CLKXTAL_D4, "clkxtal_d4", "clkxtal", 1, 4),
0436 FACTOR(CLK_TOP_HD_FAXI, "hd_faxi", "axi_sel", 1, 1),
0437 FACTOR(CLK_TOP_FAXI, "faxi", "axi_sel", 1, 1),
0438 FACTOR(CLK_TOP_F_FAUD_INTBUS, "f_faud_intbus", "aud_intbus_sel", 1, 1),
0439 FACTOR(CLK_TOP_AP2WBHIF_HCLK, "ap2wbhif_hclk", "syspll1_d8", 1, 1),
0440 FACTOR(CLK_TOP_10M_INFRAO, "infrao_10m", "gpt10m_sel", 1, 1),
0441 FACTOR(CLK_TOP_MSDC30_1, "msdc30_1", "msdc30_1_sel", 1, 1),
0442 FACTOR(CLK_TOP_SPI, "spi", "spi0_sel", 1, 1),
0443 FACTOR(CLK_TOP_SF, "sf", "nfi_infra_sel", 1, 1),
0444 FACTOR(CLK_TOP_FLASH, "flash", "flash_sel", 1, 1),
0445 FACTOR(CLK_TOP_TO_USB3_REF, "to_usb3_ref", "sata_sel", 1, 4),
0446 FACTOR(CLK_TOP_TO_USB3_MCU, "to_usb3_mcu", "axi_sel", 1, 1),
0447 FACTOR(CLK_TOP_TO_USB3_DMA, "to_usb3_dma", "hif_sel", 1, 1),
0448 FACTOR(CLK_TOP_FROM_TOP_AHB, "from_top_ahb", "axi_sel", 1, 1),
0449 FACTOR(CLK_TOP_FROM_TOP_AXI, "from_top_axi", "hif_sel", 1, 1),
0450 FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "sata_sel", 1, 1),
0451 FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "sata_sel", 1, 1),
0452 };
0453
0454 static const struct mtk_gate peri_clks[] = {
0455
0456 GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "pwm_qtr_26m", 2),
0457 GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "pwm_qtr_26m", 3),
0458 GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "pwm_qtr_26m", 4),
0459 GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "pwm_qtr_26m", 5),
0460 GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "pwm_qtr_26m", 6),
0461 GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "pwm_qtr_26m", 7),
0462 GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "pwm_qtr_26m", 8),
0463 GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "pwm_qtr_26m", 9),
0464 GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "faxi", 12),
0465 GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1", 14),
0466 GATE_PERI0(CLK_PERI_UART0_PD, "peri_uart0_pd", "faxi", 17),
0467 GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "faxi", 18),
0468 GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "faxi", 19),
0469 GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "faxi", 20),
0470 GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "faxi", 22),
0471 GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "faxi", 23),
0472 GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi", 28),
0473 GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "sf", 29),
0474 GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "faxi", 30),
0475 GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "faxi", 31),
0476
0477 GATE_PERI1(CLK_PERI_FLASH_PD, "peri_flash_pd", "flash", 1),
0478 };
0479
0480 static struct mtk_composite infra_muxes[] = {
0481
0482 MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents, 0x000,
0483 2, 2),
0484 };
0485
0486 static struct mtk_composite top_muxes[] = {
0487
0488 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
0489 0x040, 0, 3, 7),
0490 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
0491 0x040, 8, 1, 15),
0492 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
0493 0x040, 16, 1, 23),
0494 MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
0495 0x040, 24, 3, 31),
0496
0497 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
0498 0x050, 0, 2, 7),
0499 MUX_GATE(CLK_TOP_F10M_REF_SEL, "f10m_ref_sel", f10m_ref_parents,
0500 0x050, 8, 1, 15),
0501 MUX_GATE(CLK_TOP_NFI_INFRA_SEL, "nfi_infra_sel", nfi_infra_parents,
0502 0x050, 16, 4, 23),
0503 MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
0504 0x050, 24, 3, 31),
0505
0506 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
0507 0x060, 0, 1, 7),
0508 MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents,
0509 0x060, 8, 3, 15),
0510 MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents,
0511 0x060, 16, 3, 23),
0512 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
0513 0x060, 24, 3, 31),
0514
0515 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents,
0516 0x070, 0, 3, 7),
0517 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents,
0518 0x070, 8, 3, 15),
0519 MUX_GATE(CLK_TOP_AP2WBMCU_SEL, "ap2wbmcu_sel", ap2wbmcu_parents,
0520 0x070, 16, 3, 23),
0521 MUX_GATE(CLK_TOP_AP2WBHIF_SEL, "ap2wbhif_sel", ap2wbmcu_parents,
0522 0x070, 24, 3, 31),
0523
0524 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
0525 0x080, 0, 2, 7),
0526 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
0527 0x080, 8, 2, 15),
0528 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
0529 0x080, 16, 3, 23),
0530 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents,
0531 0x080, 24, 2, 31),
0532
0533 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents,
0534 0x090, 0, 2, 7),
0535 MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", hif_parents,
0536 0x090, 8, 3, 15),
0537 MUX_GATE(CLK_TOP_SATA_SEL, "sata_sel", sata_parents,
0538 0x090, 16, 1, 23),
0539 MUX_GATE(CLK_TOP_U2_SEL, "usb20_sel", usb20_parents,
0540 0x090, 24, 2, 31),
0541
0542 MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
0543 0x0A0, 0, 1, 7),
0544 MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud1_parents,
0545 0x0A0, 8, 1, 15),
0546 MUX_GATE(CLK_TOP_IRRX_SEL, "irrx_sel", irrx_parents,
0547 0x0A0, 16, 1, 23),
0548 MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", irrx_parents,
0549 0x0A0, 24, 1, 31),
0550
0551 MUX_GATE(CLK_TOP_SATA_MCU_SEL, "sata_mcu_sel", scp_parents,
0552 0x0B0, 0, 2, 7),
0553 MUX_GATE(CLK_TOP_PCIE0_MCU_SEL, "pcie0_mcu_sel", scp_parents,
0554 0x0B0, 8, 2, 15),
0555 MUX_GATE(CLK_TOP_PCIE1_MCU_SEL, "pcie1_mcu_sel", scp_parents,
0556 0x0B0, 16, 2, 23),
0557 MUX_GATE(CLK_TOP_SSUSB_MCU_SEL, "ssusb_mcu_sel", scp_parents,
0558 0x0B0, 24, 2, 31),
0559
0560 MUX_GATE(CLK_TOP_CRYPTO_SEL, "crypto_sel", crypto_parents,
0561 0x0C0, 0, 3, 7),
0562 MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, "sgmii_ref_1_sel", f10m_ref_parents,
0563 0x0C0, 8, 1, 15),
0564 MUX_GATE(CLK_TOP_10M_SEL, "gpt10m_sel", gpt10m_parents,
0565 0x0C0, 16, 1, 23),
0566 };
0567
0568 static struct mtk_composite peri_muxes[] = {
0569
0570 MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),
0571 };
0572
0573 static int mtk_topckgen_init(struct platform_device *pdev)
0574 {
0575 struct clk_hw_onecell_data *clk_data;
0576 void __iomem *base;
0577 struct device_node *node = pdev->dev.of_node;
0578
0579 base = devm_platform_ioremap_resource(pdev, 0);
0580 if (IS_ERR(base))
0581 return PTR_ERR(base);
0582
0583 clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
0584
0585 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
0586 clk_data);
0587
0588 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
0589 clk_data);
0590
0591 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
0592 base, &mt7629_clk_lock, clk_data);
0593
0594 clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk);
0595 clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk);
0596 clk_prepare_enable(clk_data->hws[CLK_TOP_DDRPHYCFG_SEL]->clk);
0597
0598 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0599 }
0600
0601 static int mtk_infrasys_init(struct platform_device *pdev)
0602 {
0603 struct device_node *node = pdev->dev.of_node;
0604 struct clk_hw_onecell_data *clk_data;
0605
0606 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
0607
0608 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
0609 clk_data);
0610
0611 mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
0612 clk_data);
0613
0614 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
0615 clk_data);
0616 }
0617
0618 static int mtk_pericfg_init(struct platform_device *pdev)
0619 {
0620 struct clk_hw_onecell_data *clk_data;
0621 void __iomem *base;
0622 int r;
0623 struct device_node *node = pdev->dev.of_node;
0624
0625 base = devm_platform_ioremap_resource(pdev, 0);
0626 if (IS_ERR(base))
0627 return PTR_ERR(base);
0628
0629 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
0630
0631 mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
0632 clk_data);
0633
0634 mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
0635 &mt7629_clk_lock, clk_data);
0636
0637 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0638 if (r)
0639 return r;
0640
0641 clk_prepare_enable(clk_data->hws[CLK_PERI_UART0_PD]->clk);
0642
0643 return 0;
0644 }
0645
0646 static int mtk_apmixedsys_init(struct platform_device *pdev)
0647 {
0648 struct clk_hw_onecell_data *clk_data;
0649 struct device_node *node = pdev->dev.of_node;
0650
0651 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
0652 if (!clk_data)
0653 return -ENOMEM;
0654
0655 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
0656 clk_data);
0657
0658 mtk_clk_register_gates(node, apmixed_clks,
0659 ARRAY_SIZE(apmixed_clks), clk_data);
0660
0661 clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);
0662 clk_prepare_enable(clk_data->hws[CLK_APMIXED_MAIN_CORE_EN]->clk);
0663
0664 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0665 }
0666
0667
0668 static const struct of_device_id of_match_clk_mt7629[] = {
0669 {
0670 .compatible = "mediatek,mt7629-apmixedsys",
0671 .data = mtk_apmixedsys_init,
0672 }, {
0673 .compatible = "mediatek,mt7629-infracfg",
0674 .data = mtk_infrasys_init,
0675 }, {
0676 .compatible = "mediatek,mt7629-topckgen",
0677 .data = mtk_topckgen_init,
0678 }, {
0679 .compatible = "mediatek,mt7629-pericfg",
0680 .data = mtk_pericfg_init,
0681 }, {
0682
0683 }
0684 };
0685
0686 static int clk_mt7629_probe(struct platform_device *pdev)
0687 {
0688 int (*clk_init)(struct platform_device *);
0689 int r;
0690
0691 clk_init = of_device_get_match_data(&pdev->dev);
0692 if (!clk_init)
0693 return -EINVAL;
0694
0695 r = clk_init(pdev);
0696 if (r)
0697 dev_err(&pdev->dev,
0698 "could not register clock provider: %s: %d\n",
0699 pdev->name, r);
0700
0701 return r;
0702 }
0703
0704 static struct platform_driver clk_mt7629_drv = {
0705 .probe = clk_mt7629_probe,
0706 .driver = {
0707 .name = "clk-mt7629",
0708 .of_match_table = of_match_clk_mt7629,
0709 },
0710 };
0711
0712 static int clk_mt7629_init(void)
0713 {
0714 return platform_driver_register(&clk_mt7629_drv);
0715 }
0716
0717 arch_initcall(clk_mt7629_init);
