clk/mediatek/clk-mt7629-hif.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2018 MediaTek Inc.
0004  * Author: Wenzhen Yu <Wenzhen Yu@mediatek.com>
0005  *     Ryder Lee <ryder.lee@mediatek.com>
0006  */
0007
0008 #include <linux/clk-provider.h>
0009 #include <linux/of.h>
0010 #include <linux/of_address.h>
0011 #include <linux/of_device.h>
0012 #include <linux/platform_device.h>
0013
0014 #include "clk-mtk.h"
0015 #include "clk-gate.h"
0016
0017 #include <dt-bindings/clock/mt7629-clk.h>
0018
0019 #define GATE_PCIE(_id, _name, _parent, _shift) {    \
0020         .id = _id,              \
0021         .name = _name,              \
0022         .parent_name = _parent,         \
0023         .regs = &pcie_cg_regs,          \
0024         .shift = _shift,            \
0025         .ops = &mtk_clk_gate_ops_no_setclr_inv, \
0026     }
0027
0028 #define GATE_SSUSB(_id, _name, _parent, _shift) {   \
0029         .id = _id,              \
0030         .name = _name,              \
0031         .parent_name = _parent,         \
0032         .regs = &ssusb_cg_regs,         \
0033         .shift = _shift,            \
0034         .ops = &mtk_clk_gate_ops_no_setclr_inv, \
0035     }
0036
0037 static const struct mtk_gate_regs pcie_cg_regs = {
0038     .set_ofs = 0x30,
0039     .clr_ofs = 0x30,
0040     .sta_ofs = 0x30,
0041 };
0042
0043 static const struct mtk_gate_regs ssusb_cg_regs = {
0044     .set_ofs = 0x30,
0045     .clr_ofs = 0x30,
0046     .sta_ofs = 0x30,
0047 };
0048
0049 static const struct mtk_gate ssusb_clks[] = {
0050     GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, "ssusb_u2_phy_1p",
0051            "to_u2_phy_1p", 0),
0052     GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, "ssusb_u2_phy_en", "to_u2_phy", 1),
0053     GATE_SSUSB(CLK_SSUSB_REF_EN, "ssusb_ref_en", "to_usb3_ref", 5),
0054     GATE_SSUSB(CLK_SSUSB_SYS_EN, "ssusb_sys_en", "to_usb3_sys", 6),
0055     GATE_SSUSB(CLK_SSUSB_MCU_EN, "ssusb_mcu_en", "to_usb3_mcu", 7),
0056     GATE_SSUSB(CLK_SSUSB_DMA_EN, "ssusb_dma_en", "to_usb3_dma", 8),
0057 };
0058
0059 static const struct mtk_gate pcie_clks[] = {
0060     GATE_PCIE(CLK_PCIE_P1_AUX_EN, "pcie_p1_aux_en", "p1_1mhz", 12),
0061     GATE_PCIE(CLK_PCIE_P1_OBFF_EN, "pcie_p1_obff_en", "free_run_4mhz", 13),
0062     GATE_PCIE(CLK_PCIE_P1_AHB_EN, "pcie_p1_ahb_en", "from_top_ahb", 14),
0063     GATE_PCIE(CLK_PCIE_P1_AXI_EN, "pcie_p1_axi_en", "from_top_axi", 15),
0064     GATE_PCIE(CLK_PCIE_P1_MAC_EN, "pcie_p1_mac_en", "pcie1_mac_en", 16),
0065     GATE_PCIE(CLK_PCIE_P1_PIPE_EN, "pcie_p1_pipe_en", "pcie1_pipe_en", 17),
0066     GATE_PCIE(CLK_PCIE_P0_AUX_EN, "pcie_p0_aux_en", "p0_1mhz", 18),
0067     GATE_PCIE(CLK_PCIE_P0_OBFF_EN, "pcie_p0_obff_en", "free_run_4mhz", 19),
0068     GATE_PCIE(CLK_PCIE_P0_AHB_EN, "pcie_p0_ahb_en", "from_top_ahb", 20),
0069     GATE_PCIE(CLK_PCIE_P0_AXI_EN, "pcie_p0_axi_en", "from_top_axi", 21),
0070     GATE_PCIE(CLK_PCIE_P0_MAC_EN, "pcie_p0_mac_en", "pcie0_mac_en", 22),
0071     GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23),
0072 };
0073
0074 static u16 rst_ofs[] = { 0x34, };
0075
0076 static const struct mtk_clk_rst_desc clk_rst_desc = {
0077     .version = MTK_RST_SIMPLE,
0078     .rst_bank_ofs = rst_ofs,
0079     .rst_bank_nr = ARRAY_SIZE(rst_ofs),
0080 };
0081
0082 static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
0083 {
0084     struct clk_hw_onecell_data *clk_data;
0085     struct device_node *node = pdev->dev.of_node;
0086     int r;
0087
0088     clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
0089
0090     mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
0091                    clk_data);
0092
0093     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0094     if (r)
0095         dev_err(&pdev->dev,
0096             "could not register clock provider: %s: %d\n",
0097             pdev->name, r);
0098
0099     mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
0100
0101     return r;
0102 }
0103
0104 static int clk_mt7629_pciesys_init(struct platform_device *pdev)
0105 {
0106     struct clk_hw_onecell_data *clk_data;
0107     struct device_node *node = pdev->dev.of_node;
0108     int r;
0109
0110     clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
0111
0112     mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
0113                    clk_data);
0114
0115     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0116     if (r)
0117         dev_err(&pdev->dev,
0118             "could not register clock provider: %s: %d\n",
0119             pdev->name, r);
0120
0121     mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
0122
0123     return r;
0124 }
0125
0126 static const struct of_device_id of_match_clk_mt7629_hif[] = {
0127     {
0128         .compatible = "mediatek,mt7629-pciesys",
0129         .data = clk_mt7629_pciesys_init,
0130     }, {
0131         .compatible = "mediatek,mt7629-ssusbsys",
0132         .data = clk_mt7629_ssusbsys_init,
0133     }, {
0134         /* sentinel */
0135     }
0136 };
0137
0138 static int clk_mt7629_hif_probe(struct platform_device *pdev)
0139 {
0140     int (*clk_init)(struct platform_device *);
0141     int r;
0142
0143     clk_init = of_device_get_match_data(&pdev->dev);
0144     if (!clk_init)
0145         return -EINVAL;
0146
0147     r = clk_init(pdev);
0148     if (r)
0149         dev_err(&pdev->dev,
0150             "could not register clock provider: %s: %d\n",
0151             pdev->name, r);
0152
0153     return r;
0154 }
0155
0156 static struct platform_driver clk_mt7629_hif_drv = {
0157     .probe = clk_mt7629_hif_probe,
0158     .driver = {
0159         .name = "clk-mt7629-hif",
0160         .of_match_table = of_match_clk_mt7629_hif,
0161     },
0162 };
0163
0164 builtin_platform_driver(clk_mt7629_hif_drv);