clk/mediatek/clk-mt7629-eth.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2018 MediaTek Inc.
0004  * Author: Wenzhen Yu <Wenzhen Yu@mediatek.com>
0005  *     Ryder Lee <ryder.lee@mediatek.com>
0006  */
0007
0008 #include <linux/clk-provider.h>
0009 #include <linux/of.h>
0010 #include <linux/of_address.h>
0011 #include <linux/of_device.h>
0012 #include <linux/platform_device.h>
0013
0014 #include "clk-mtk.h"
0015 #include "clk-gate.h"
0016
0017 #include <dt-bindings/clock/mt7629-clk.h>
0018
0019 #define GATE_ETH(_id, _name, _parent, _shift) {     \
0020         .id = _id,              \
0021         .name = _name,              \
0022         .parent_name = _parent,         \
0023         .regs = &eth_cg_regs,           \
0024         .shift = _shift,            \
0025         .ops = &mtk_clk_gate_ops_no_setclr_inv, \
0026     }
0027
0028 static const struct mtk_gate_regs eth_cg_regs = {
0029     .set_ofs = 0x30,
0030     .clr_ofs = 0x30,
0031     .sta_ofs = 0x30,
0032 };
0033
0034 static const struct mtk_gate eth_clks[] = {
0035     GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "eth2pll", 6),
0036     GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7),
0037     GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8),
0038     GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9),
0039     GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 16),
0040 };
0041
0042 static const struct mtk_gate_regs sgmii_cg_regs = {
0043     .set_ofs = 0xE4,
0044     .clr_ofs = 0xE4,
0045     .sta_ofs = 0xE4,
0046 };
0047
0048 #define GATE_SGMII(_id, _name, _parent, _shift) {   \
0049         .id = _id,              \
0050         .name = _name,              \
0051         .parent_name = _parent,         \
0052         .regs = &sgmii_cg_regs,         \
0053         .shift = _shift,            \
0054         .ops = &mtk_clk_gate_ops_no_setclr_inv, \
0055     }
0056
0057 static const struct mtk_gate sgmii_clks[2][4] = {
0058     {
0059         GATE_SGMII(CLK_SGMII_TX_EN, "sgmii_tx_en",
0060                "ssusb_tx250m", 2),
0061         GATE_SGMII(CLK_SGMII_RX_EN, "sgmii_rx_en",
0062                "ssusb_eq_rx250m", 3),
0063         GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref",
0064                "ssusb_cdr_ref", 4),
0065         GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb",
0066                "ssusb_cdr_fb", 5),
0067     }, {
0068         GATE_SGMII(CLK_SGMII_TX_EN, "sgmii_tx_en1",
0069                "ssusb_tx250m", 2),
0070         GATE_SGMII(CLK_SGMII_RX_EN, "sgmii_rx_en1",
0071                "ssusb_eq_rx250m", 3),
0072         GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref1",
0073                "ssusb_cdr_ref", 4),
0074         GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb1",
0075                "ssusb_cdr_fb", 5),
0076     }
0077 };
0078
0079 static u16 rst_ofs[] = { 0x34, };
0080
0081 static const struct mtk_clk_rst_desc clk_rst_desc = {
0082     .version = MTK_RST_SIMPLE,
0083     .rst_bank_ofs = rst_ofs,
0084     .rst_bank_nr = ARRAY_SIZE(rst_ofs),
0085 };
0086
0087 static int clk_mt7629_ethsys_init(struct platform_device *pdev)
0088 {
0089     struct clk_hw_onecell_data *clk_data;
0090     struct device_node *node = pdev->dev.of_node;
0091     int r;
0092
0093     clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
0094
0095     mtk_clk_register_gates(node, eth_clks, CLK_ETH_NR_CLK, clk_data);
0096
0097     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0098     if (r)
0099         dev_err(&pdev->dev,
0100             "could not register clock provider: %s: %d\n",
0101             pdev->name, r);
0102
0103     mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
0104
0105     return r;
0106 }
0107
0108 static int clk_mt7629_sgmiisys_init(struct platform_device *pdev)
0109 {
0110     struct clk_hw_onecell_data *clk_data;
0111     struct device_node *node = pdev->dev.of_node;
0112     static int id;
0113     int r;
0114
0115     clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
0116
0117     mtk_clk_register_gates(node, sgmii_clks[id++], CLK_SGMII_NR_CLK,
0118                    clk_data);
0119
0120     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0121     if (r)
0122         dev_err(&pdev->dev,
0123             "could not register clock provider: %s: %d\n",
0124             pdev->name, r);
0125
0126     return r;
0127 }
0128
0129 static const struct of_device_id of_match_clk_mt7629_eth[] = {
0130     {
0131         .compatible = "mediatek,mt7629-ethsys",
0132         .data = clk_mt7629_ethsys_init,
0133     }, {
0134         .compatible = "mediatek,mt7629-sgmiisys",
0135         .data = clk_mt7629_sgmiisys_init,
0136     }, {
0137         /* sentinel */
0138     }
0139 };
0140
0141 static int clk_mt7629_eth_probe(struct platform_device *pdev)
0142 {
0143     int (*clk_init)(struct platform_device *);
0144     int r;
0145
0146     clk_init = of_device_get_match_data(&pdev->dev);
0147     if (!clk_init)
0148         return -EINVAL;
0149
0150     r = clk_init(pdev);
0151     if (r)
0152         dev_err(&pdev->dev,
0153             "could not register clock provider: %s: %d\n",
0154             pdev->name, r);
0155
0156     return r;
0157 }
0158
0159 static struct platform_driver clk_mt7629_eth_drv = {
0160     .probe = clk_mt7629_eth_probe,
0161     .driver = {
0162         .name = "clk-mt7629-eth",
0163         .of_match_table = of_match_clk_mt7629_eth,
0164     },
0165 };
0166
0167 builtin_platform_driver(clk_mt7629_eth_drv);