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0008 #include <linux/clk-provider.h>
0009 #include <linux/of.h>
0010 #include <linux/of_address.h>
0011 #include <linux/of_device.h>
0012 #include <linux/platform_device.h>
0013
0014 #include "clk-cpumux.h"
0015 #include "clk-gate.h"
0016 #include "clk-mtk.h"
0017 #include "clk-pll.h"
0018
0019 #include <dt-bindings/clock/mt7622-clk.h>
0020 #include <linux/clk.h> /* for consumer */
0021
0022 #define MT7622_PLL_FMAX (2500UL * MHZ)
0023 #define CON0_MT7622_RST_BAR BIT(27)
0024
0025 #define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
0026 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
0027 _pcw_shift, _div_table, _parent_name) { \
0028 .id = _id, \
0029 .name = _name, \
0030 .reg = _reg, \
0031 .pwr_reg = _pwr_reg, \
0032 .en_mask = _en_mask, \
0033 .flags = _flags, \
0034 .rst_bar_mask = CON0_MT7622_RST_BAR, \
0035 .fmax = MT7622_PLL_FMAX, \
0036 .pcwbits = _pcwbits, \
0037 .pd_reg = _pd_reg, \
0038 .pd_shift = _pd_shift, \
0039 .tuner_reg = _tuner_reg, \
0040 .pcw_reg = _pcw_reg, \
0041 .pcw_shift = _pcw_shift, \
0042 .div_table = _div_table, \
0043 .parent_name = _parent_name, \
0044 }
0045
0046 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
0047 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
0048 _pcw_shift) \
0049 PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
0050 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
0051 NULL, "clkxtal")
0052
0053 #define GATE_APMIXED(_id, _name, _parent, _shift) { \
0054 .id = _id, \
0055 .name = _name, \
0056 .parent_name = _parent, \
0057 .regs = &apmixed_cg_regs, \
0058 .shift = _shift, \
0059 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
0060 }
0061
0062 #define GATE_INFRA(_id, _name, _parent, _shift) { \
0063 .id = _id, \
0064 .name = _name, \
0065 .parent_name = _parent, \
0066 .regs = &infra_cg_regs, \
0067 .shift = _shift, \
0068 .ops = &mtk_clk_gate_ops_setclr, \
0069 }
0070
0071 #define GATE_TOP0(_id, _name, _parent, _shift) { \
0072 .id = _id, \
0073 .name = _name, \
0074 .parent_name = _parent, \
0075 .regs = &top0_cg_regs, \
0076 .shift = _shift, \
0077 .ops = &mtk_clk_gate_ops_no_setclr, \
0078 }
0079
0080 #define GATE_TOP1(_id, _name, _parent, _shift) { \
0081 .id = _id, \
0082 .name = _name, \
0083 .parent_name = _parent, \
0084 .regs = &top1_cg_regs, \
0085 .shift = _shift, \
0086 .ops = &mtk_clk_gate_ops_no_setclr, \
0087 }
0088
0089 #define GATE_PERI0(_id, _name, _parent, _shift) { \
0090 .id = _id, \
0091 .name = _name, \
0092 .parent_name = _parent, \
0093 .regs = &peri0_cg_regs, \
0094 .shift = _shift, \
0095 .ops = &mtk_clk_gate_ops_setclr, \
0096 }
0097
0098 #define GATE_PERI1(_id, _name, _parent, _shift) { \
0099 .id = _id, \
0100 .name = _name, \
0101 .parent_name = _parent, \
0102 .regs = &peri1_cg_regs, \
0103 .shift = _shift, \
0104 .ops = &mtk_clk_gate_ops_setclr, \
0105 }
0106
0107 static DEFINE_SPINLOCK(mt7622_clk_lock);
0108
0109 static const char * const infra_mux1_parents[] = {
0110 "clkxtal",
0111 "armpll",
0112 "main_core_en",
0113 "armpll"
0114 };
0115
0116 static const char * const axi_parents[] = {
0117 "clkxtal",
0118 "syspll1_d2",
0119 "syspll_d5",
0120 "syspll1_d4",
0121 "univpll_d5",
0122 "univpll2_d2",
0123 "univpll_d7"
0124 };
0125
0126 static const char * const mem_parents[] = {
0127 "clkxtal",
0128 "dmpll_ck"
0129 };
0130
0131 static const char * const ddrphycfg_parents[] = {
0132 "clkxtal",
0133 "syspll1_d8"
0134 };
0135
0136 static const char * const eth_parents[] = {
0137 "clkxtal",
0138 "syspll1_d2",
0139 "univpll1_d2",
0140 "syspll1_d4",
0141 "univpll_d5",
0142 "clk_null",
0143 "univpll_d7"
0144 };
0145
0146 static const char * const pwm_parents[] = {
0147 "clkxtal",
0148 "univpll2_d4"
0149 };
0150
0151 static const char * const f10m_ref_parents[] = {
0152 "clkxtal",
0153 "syspll4_d16"
0154 };
0155
0156 static const char * const nfi_infra_parents[] = {
0157 "clkxtal",
0158 "clkxtal",
0159 "clkxtal",
0160 "clkxtal",
0161 "clkxtal",
0162 "clkxtal",
0163 "clkxtal",
0164 "clkxtal",
0165 "univpll2_d8",
0166 "syspll1_d8",
0167 "univpll1_d8",
0168 "syspll4_d2",
0169 "univpll2_d4",
0170 "univpll3_d2",
0171 "syspll1_d4"
0172 };
0173
0174 static const char * const flash_parents[] = {
0175 "clkxtal",
0176 "univpll_d80_d4",
0177 "syspll2_d8",
0178 "syspll3_d4",
0179 "univpll3_d4",
0180 "univpll1_d8",
0181 "syspll2_d4",
0182 "univpll2_d4"
0183 };
0184
0185 static const char * const uart_parents[] = {
0186 "clkxtal",
0187 "univpll2_d8"
0188 };
0189
0190 static const char * const spi0_parents[] = {
0191 "clkxtal",
0192 "syspll3_d2",
0193 "clkxtal",
0194 "syspll2_d4",
0195 "syspll4_d2",
0196 "univpll2_d4",
0197 "univpll1_d8",
0198 "clkxtal"
0199 };
0200
0201 static const char * const spi1_parents[] = {
0202 "clkxtal",
0203 "syspll3_d2",
0204 "clkxtal",
0205 "syspll4_d4",
0206 "syspll4_d2",
0207 "univpll2_d4",
0208 "univpll1_d8",
0209 "clkxtal"
0210 };
0211
0212 static const char * const msdc30_0_parents[] = {
0213 "clkxtal",
0214 "univpll2_d16",
0215 "univ48m"
0216 };
0217
0218 static const char * const a1sys_hp_parents[] = {
0219 "clkxtal",
0220 "aud1pll_ck",
0221 "aud2pll_ck",
0222 "clkxtal"
0223 };
0224
0225 static const char * const intdir_parents[] = {
0226 "clkxtal",
0227 "syspll_d2",
0228 "univpll_d2",
0229 "sgmiipll_ck"
0230 };
0231
0232 static const char * const aud_intbus_parents[] = {
0233 "clkxtal",
0234 "syspll1_d4",
0235 "syspll4_d2",
0236 "syspll3_d2"
0237 };
0238
0239 static const char * const pmicspi_parents[] = {
0240 "clkxtal",
0241 "clk_null",
0242 "clk_null",
0243 "clk_null",
0244 "clk_null",
0245 "univpll2_d16"
0246 };
0247
0248 static const char * const atb_parents[] = {
0249 "clkxtal",
0250 "syspll1_d2",
0251 "syspll_d5"
0252 };
0253
0254 static const char * const audio_parents[] = {
0255 "clkxtal",
0256 "syspll3_d4",
0257 "syspll4_d4",
0258 "univpll1_d16"
0259 };
0260
0261 static const char * const usb20_parents[] = {
0262 "clkxtal",
0263 "univpll3_d4",
0264 "syspll1_d8",
0265 "clkxtal"
0266 };
0267
0268 static const char * const aud1_parents[] = {
0269 "clkxtal",
0270 "aud1pll_ck"
0271 };
0272
0273 static const char * const aud2_parents[] = {
0274 "clkxtal",
0275 "aud2pll_ck"
0276 };
0277
0278 static const char * const asm_l_parents[] = {
0279 "clkxtal",
0280 "syspll_d5",
0281 "univpll2_d2",
0282 "univpll2_d4"
0283 };
0284
0285 static const char * const apll1_ck_parents[] = {
0286 "aud1_sel",
0287 "aud2_sel"
0288 };
0289
0290 static const char * const peribus_ck_parents[] = {
0291 "syspll1_d8",
0292 "syspll1_d4"
0293 };
0294
0295 static const struct mtk_gate_regs apmixed_cg_regs = {
0296 .set_ofs = 0x8,
0297 .clr_ofs = 0x8,
0298 .sta_ofs = 0x8,
0299 };
0300
0301 static const struct mtk_gate_regs infra_cg_regs = {
0302 .set_ofs = 0x40,
0303 .clr_ofs = 0x44,
0304 .sta_ofs = 0x48,
0305 };
0306
0307 static const struct mtk_gate_regs top0_cg_regs = {
0308 .set_ofs = 0x120,
0309 .clr_ofs = 0x120,
0310 .sta_ofs = 0x120,
0311 };
0312
0313 static const struct mtk_gate_regs top1_cg_regs = {
0314 .set_ofs = 0x128,
0315 .clr_ofs = 0x128,
0316 .sta_ofs = 0x128,
0317 };
0318
0319 static const struct mtk_gate_regs peri0_cg_regs = {
0320 .set_ofs = 0x8,
0321 .clr_ofs = 0x10,
0322 .sta_ofs = 0x18,
0323 };
0324
0325 static const struct mtk_gate_regs peri1_cg_regs = {
0326 .set_ofs = 0xC,
0327 .clr_ofs = 0x14,
0328 .sta_ofs = 0x1C,
0329 };
0330
0331 static const struct mtk_pll_data plls[] = {
0332 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0,
0333 PLL_AO, 21, 0x0204, 24, 0, 0x0204, 0),
0334 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0,
0335 HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
0336 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0,
0337 HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
0338 PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0,
0339 0, 21, 0x0300, 1, 0, 0x0304, 0),
0340 PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0,
0341 0, 21, 0x0314, 1, 0, 0x0318, 0),
0342 PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0,
0343 0, 31, 0x0324, 1, 0, 0x0328, 0),
0344 PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0,
0345 0, 31, 0x0334, 1, 0, 0x0338, 0),
0346 PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0,
0347 0, 21, 0x0344, 1, 0, 0x0348, 0),
0348 PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0,
0349 0, 21, 0x0358, 1, 0, 0x035C, 0),
0350 };
0351
0352 static const struct mtk_gate apmixed_clks[] = {
0353 GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5),
0354 };
0355
0356 static const struct mtk_gate infra_clks[] = {
0357 GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "axi_sel", 0),
0358 GATE_INFRA(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 2),
0359 GATE_INFRA(CLK_INFRA_AUDIO_PD, "infra_audio_pd", "aud_intbus_sel", 5),
0360 GATE_INFRA(CLK_INFRA_IRRX_PD, "infra_irrx_pd", "irrx_sel", 16),
0361 GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "f10m_ref_sel", 18),
0362 GATE_INFRA(CLK_INFRA_PMIC_PD, "infra_pmic_pd", "pmicspi_sel", 22),
0363 };
0364
0365 static const struct mtk_fixed_clk top_fixed_clks[] = {
0366 FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal",
0367 31250000),
0368 FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, "to_u2_phy_1p", "clkxtal",
0369 31250000),
0370 FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, "pcie0_pipe_en", "clkxtal",
0371 125000000),
0372 FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, "pcie1_pipe_en", "clkxtal",
0373 125000000),
0374 FIXED_CLK(CLK_TOP_SSUSB_TX250M, "ssusb_tx250m", "clkxtal",
0375 250000000),
0376 FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, "ssusb_eq_rx250m", "clkxtal",
0377 250000000),
0378 FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, "ssusb_cdr_ref", "clkxtal",
0379 33333333),
0380 FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, "ssusb_cdr_fb", "clkxtal",
0381 50000000),
0382 FIXED_CLK(CLK_TOP_SATA_ASIC, "sata_asic", "clkxtal",
0383 50000000),
0384 FIXED_CLK(CLK_TOP_SATA_RBC, "sata_rbc", "clkxtal",
0385 50000000),
0386 };
0387
0388 static const struct mtk_fixed_factor top_divs[] = {
0389 FACTOR(CLK_TOP_TO_USB3_SYS, "to_usb3_sys", "eth1pll", 1, 4),
0390 FACTOR(CLK_TOP_P1_1MHZ, "p1_1mhz", "eth1pll", 1, 500),
0391 FACTOR(CLK_TOP_4MHZ, "free_run_4mhz", "eth1pll", 1, 125),
0392 FACTOR(CLK_TOP_P0_1MHZ, "p0_1mhz", "eth1pll", 1, 500),
0393 FACTOR(CLK_TOP_TXCLK_SRC_PRE, "txclk_src_pre", "sgmiipll_d2", 1, 1),
0394 FACTOR(CLK_TOP_RTC, "rtc", "clkxtal", 1, 1024),
0395 FACTOR(CLK_TOP_MEMPLL, "mempll", "clkxtal", 32, 1),
0396 FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
0397 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
0398 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4),
0399 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8),
0400 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16),
0401 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12),
0402 FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24),
0403 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
0404 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10),
0405 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20),
0406 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
0407 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28),
0408 FACTOR(CLK_TOP_SYSPLL4_D16, "syspll4_d16", "mainpll", 1, 112),
0409 FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2),
0410 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
0411 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
0412 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8),
0413 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16),
0414 FACTOR(CLK_TOP_UNIVPLL1_D16, "univpll1_d16", "univpll", 1, 32),
0415 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6),
0416 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12),
0417 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24),
0418 FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll", 1, 48),
0419 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
0420 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10),
0421 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20),
0422 FACTOR(CLK_TOP_UNIVPLL3_D16, "univpll3_d16", "univpll", 1, 80),
0423 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
0424 FACTOR(CLK_TOP_UNIVPLL_D80_D4, "univpll_d80_d4", "univpll", 1, 320),
0425 FACTOR(CLK_TOP_UNIV48M, "univ48m", "univpll", 1, 25),
0426 FACTOR(CLK_TOP_SGMIIPLL, "sgmiipll_ck", "sgmipll", 1, 1),
0427 FACTOR(CLK_TOP_SGMIIPLL_D2, "sgmiipll_d2", "sgmipll", 1, 2),
0428 FACTOR(CLK_TOP_AUD1PLL, "aud1pll_ck", "aud1pll", 1, 1),
0429 FACTOR(CLK_TOP_AUD2PLL, "aud2pll_ck", "aud2pll", 1, 1),
0430 FACTOR(CLK_TOP_AUD_I2S2_MCK, "aud_i2s2_mck", "i2s2_mck_sel", 1, 2),
0431 FACTOR(CLK_TOP_TO_USB3_REF, "to_usb3_ref", "univpll2_d4", 1, 4),
0432 FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "univpll1_d4", 1, 1),
0433 FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "univpll1_d4", 1, 1),
0434 FACTOR(CLK_TOP_ETH_500M, "eth_500m", "eth1pll", 1, 1),
0435 };
0436
0437 static const struct mtk_gate top_clks[] = {
0438
0439 GATE_TOP0(CLK_TOP_APLL1_DIV_PD, "apll1_ck_div_pd", "apll1_ck_div", 0),
0440 GATE_TOP0(CLK_TOP_APLL2_DIV_PD, "apll2_ck_div_pd", "apll2_ck_div", 1),
0441 GATE_TOP0(CLK_TOP_I2S0_MCK_DIV_PD, "i2s0_mck_div_pd", "i2s0_mck_div",
0442 2),
0443 GATE_TOP0(CLK_TOP_I2S1_MCK_DIV_PD, "i2s1_mck_div_pd", "i2s1_mck_div",
0444 3),
0445 GATE_TOP0(CLK_TOP_I2S2_MCK_DIV_PD, "i2s2_mck_div_pd", "i2s2_mck_div",
0446 4),
0447 GATE_TOP0(CLK_TOP_I2S3_MCK_DIV_PD, "i2s3_mck_div_pd", "i2s3_mck_div",
0448 5),
0449
0450
0451 GATE_TOP1(CLK_TOP_A1SYS_HP_DIV_PD, "a1sys_div_pd", "a1sys_div", 0),
0452 GATE_TOP1(CLK_TOP_A2SYS_HP_DIV_PD, "a2sys_div_pd", "a2sys_div", 16),
0453 };
0454
0455 static const struct mtk_clk_divider top_adj_divs[] = {
0456 DIV_ADJ(CLK_TOP_APLL1_DIV, "apll1_ck_div", "apll1_ck_sel",
0457 0x120, 24, 3),
0458 DIV_ADJ(CLK_TOP_APLL2_DIV, "apll2_ck_div", "apll2_ck_sel",
0459 0x120, 28, 3),
0460 DIV_ADJ(CLK_TOP_I2S0_MCK_DIV, "i2s0_mck_div", "i2s0_mck_sel",
0461 0x124, 0, 7),
0462 DIV_ADJ(CLK_TOP_I2S1_MCK_DIV, "i2s1_mck_div", "i2s1_mck_sel",
0463 0x124, 8, 7),
0464 DIV_ADJ(CLK_TOP_I2S2_MCK_DIV, "i2s2_mck_div", "aud_i2s2_mck",
0465 0x124, 16, 7),
0466 DIV_ADJ(CLK_TOP_I2S3_MCK_DIV, "i2s3_mck_div", "i2s3_mck_sel",
0467 0x124, 24, 7),
0468 DIV_ADJ(CLK_TOP_A1SYS_HP_DIV, "a1sys_div", "a1sys_hp_sel",
0469 0x128, 8, 7),
0470 DIV_ADJ(CLK_TOP_A2SYS_HP_DIV, "a2sys_div", "a2sys_hp_sel",
0471 0x128, 24, 7),
0472 };
0473
0474 static const struct mtk_gate peri_clks[] = {
0475
0476 GATE_PERI0(CLK_PERI_THERM_PD, "peri_therm_pd", "axi_sel", 1),
0477 GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "clkxtal", 2),
0478 GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "clkxtal", 3),
0479 GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "clkxtal", 4),
0480 GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "clkxtal", 5),
0481 GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "clkxtal", 6),
0482 GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "clkxtal", 7),
0483 GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "clkxtal", 8),
0484 GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "clkxtal", 9),
0485 GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "axi_sel", 12),
0486 GATE_PERI0(CLK_PERI_MSDC30_0_PD, "peri_msdc30_0", "msdc30_0_sel", 13),
0487 GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1_sel", 14),
0488 GATE_PERI0(CLK_PERI_UART0_PD, "peri_uart0_pd", "axi_sel", 17),
0489 GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "axi_sel", 18),
0490 GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "axi_sel", 19),
0491 GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "axi_sel", 20),
0492 GATE_PERI0(CLK_PERI_UART4_PD, "peri_uart4_pd", "axi_sel", 21),
0493 GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "axi_sel", 22),
0494 GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "axi_sel", 23),
0495 GATE_PERI0(CLK_PERI_I2C1_PD, "peri_i2c1_pd", "axi_sel", 24),
0496 GATE_PERI0(CLK_PERI_I2C2_PD, "peri_i2c2_pd", "axi_sel", 25),
0497 GATE_PERI0(CLK_PERI_SPI1_PD, "peri_spi1_pd", "spi1_sel", 26),
0498 GATE_PERI0(CLK_PERI_AUXADC_PD, "peri_auxadc_pd", "clkxtal", 27),
0499 GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi0_sel", 28),
0500 GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "nfi_infra_sel", 29),
0501 GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "axi_sel", 30),
0502 GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "axi_sel", 31),
0503
0504
0505 GATE_PERI1(CLK_PERI_FLASH_PD, "peri_flash_pd", "flash_sel", 1),
0506 GATE_PERI1(CLK_PERI_IRTX_PD, "peri_irtx_pd", "irtx_sel", 2),
0507 };
0508
0509 static struct mtk_composite infra_muxes[] = {
0510 MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents,
0511 0x000, 2, 2),
0512 };
0513
0514 static struct mtk_composite top_muxes[] = {
0515
0516 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
0517 0x040, 0, 3, 7),
0518 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
0519 0x040, 8, 1, 15),
0520 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
0521 0x040, 16, 1, 23),
0522 MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
0523 0x040, 24, 3, 31),
0524
0525
0526 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
0527 0x050, 0, 2, 7),
0528 MUX_GATE(CLK_TOP_F10M_REF_SEL, "f10m_ref_sel", f10m_ref_parents,
0529 0x050, 8, 1, 15),
0530 MUX_GATE(CLK_TOP_NFI_INFRA_SEL, "nfi_infra_sel", nfi_infra_parents,
0531 0x050, 16, 4, 23),
0532 MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
0533 0x050, 24, 3, 31),
0534
0535
0536 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
0537 0x060, 0, 1, 7),
0538 MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents,
0539 0x060, 8, 3, 15),
0540 MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents,
0541 0x060, 16, 3, 23),
0542 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
0543 0x060, 24, 3, 31),
0544
0545
0546 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents,
0547 0x070, 0, 3, 7),
0548 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_0_parents,
0549 0x070, 8, 3, 15),
0550 MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", a1sys_hp_parents,
0551 0x070, 16, 2, 23),
0552 MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel", a1sys_hp_parents,
0553 0x070, 24, 2, 31),
0554
0555
0556 MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents,
0557 0x080, 0, 2, 7),
0558 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
0559 0x080, 8, 2, 15),
0560 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
0561 0x080, 16, 3, 23),
0562 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", ddrphycfg_parents,
0563 0x080, 24, 2, 31),
0564
0565
0566 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents,
0567 0x090, 0, 2, 7),
0568 MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", eth_parents,
0569 0x090, 8, 3, 15),
0570 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
0571 0x090, 16, 2, 23),
0572 MUX_GATE(CLK_TOP_U2_SEL, "usb20_sel", usb20_parents,
0573 0x090, 24, 2, 31),
0574
0575
0576 MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
0577 0x0A0, 0, 1, 7),
0578 MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
0579 0x0A0, 8, 1, 15),
0580 MUX_GATE(CLK_TOP_IRRX_SEL, "irrx_sel", f10m_ref_parents,
0581 0x0A0, 16, 1, 23),
0582 MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", f10m_ref_parents,
0583 0x0A0, 24, 1, 31),
0584
0585
0586 MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel", asm_l_parents,
0587 0x0B0, 0, 2, 7),
0588 MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_l_parents,
0589 0x0B0, 8, 2, 15),
0590 MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_l_parents,
0591 0x0B0, 16, 2, 23),
0592
0593
0594 MUX(CLK_TOP_APLL1_SEL, "apll1_ck_sel", apll1_ck_parents,
0595 0x120, 6, 1),
0596 MUX(CLK_TOP_APLL2_SEL, "apll2_ck_sel", apll1_ck_parents,
0597 0x120, 7, 1),
0598 MUX(CLK_TOP_I2S0_MCK_SEL, "i2s0_mck_sel", apll1_ck_parents,
0599 0x120, 8, 1),
0600 MUX(CLK_TOP_I2S1_MCK_SEL, "i2s1_mck_sel", apll1_ck_parents,
0601 0x120, 9, 1),
0602 MUX(CLK_TOP_I2S2_MCK_SEL, "i2s2_mck_sel", apll1_ck_parents,
0603 0x120, 10, 1),
0604 MUX(CLK_TOP_I2S3_MCK_SEL, "i2s3_mck_sel", apll1_ck_parents,
0605 0x120, 11, 1),
0606 };
0607
0608 static struct mtk_composite peri_muxes[] = {
0609
0610 MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),
0611 };
0612
0613 static u16 infrasys_rst_ofs[] = { 0x30, };
0614 static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
0615
0616 static const struct mtk_clk_rst_desc clk_rst_desc[] = {
0617
0618 {
0619 .version = MTK_RST_SIMPLE,
0620 .rst_bank_ofs = infrasys_rst_ofs,
0621 .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
0622 },
0623
0624 {
0625 .version = MTK_RST_SIMPLE,
0626 .rst_bank_ofs = pericfg_rst_ofs,
0627 .rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
0628 },
0629 };
0630
0631 static int mtk_topckgen_init(struct platform_device *pdev)
0632 {
0633 struct clk_hw_onecell_data *clk_data;
0634 void __iomem *base;
0635 struct device_node *node = pdev->dev.of_node;
0636
0637 base = devm_platform_ioremap_resource(pdev, 0);
0638 if (IS_ERR(base))
0639 return PTR_ERR(base);
0640
0641 clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
0642
0643 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
0644 clk_data);
0645
0646 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
0647 clk_data);
0648
0649 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
0650 base, &mt7622_clk_lock, clk_data);
0651
0652 mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
0653 base, &mt7622_clk_lock, clk_data);
0654
0655 mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
0656 clk_data);
0657
0658 clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk);
0659 clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk);
0660 clk_prepare_enable(clk_data->hws[CLK_TOP_DDRPHYCFG_SEL]->clk);
0661
0662 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0663 }
0664
0665 static int mtk_infrasys_init(struct platform_device *pdev)
0666 {
0667 struct device_node *node = pdev->dev.of_node;
0668 struct clk_hw_onecell_data *clk_data;
0669 int r;
0670
0671 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
0672
0673 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
0674 clk_data);
0675
0676 mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
0677 clk_data);
0678
0679 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
0680 clk_data);
0681 if (r)
0682 return r;
0683
0684 mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
0685
0686 return 0;
0687 }
0688
0689 static int mtk_apmixedsys_init(struct platform_device *pdev)
0690 {
0691 struct clk_hw_onecell_data *clk_data;
0692 struct device_node *node = pdev->dev.of_node;
0693
0694 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
0695 if (!clk_data)
0696 return -ENOMEM;
0697
0698 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
0699 clk_data);
0700
0701 mtk_clk_register_gates(node, apmixed_clks,
0702 ARRAY_SIZE(apmixed_clks), clk_data);
0703
0704 clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);
0705 clk_prepare_enable(clk_data->hws[CLK_APMIXED_MAIN_CORE_EN]->clk);
0706
0707 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0708 }
0709
0710 static int mtk_pericfg_init(struct platform_device *pdev)
0711 {
0712 struct clk_hw_onecell_data *clk_data;
0713 void __iomem *base;
0714 int r;
0715 struct device_node *node = pdev->dev.of_node;
0716
0717 base = devm_platform_ioremap_resource(pdev, 0);
0718 if (IS_ERR(base))
0719 return PTR_ERR(base);
0720
0721 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
0722
0723 mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
0724 clk_data);
0725
0726 mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
0727 &mt7622_clk_lock, clk_data);
0728
0729 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0730 if (r)
0731 return r;
0732
0733 clk_prepare_enable(clk_data->hws[CLK_PERI_UART0_PD]->clk);
0734
0735 mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
0736
0737 return 0;
0738 }
0739
0740 static const struct of_device_id of_match_clk_mt7622[] = {
0741 {
0742 .compatible = "mediatek,mt7622-apmixedsys",
0743 .data = mtk_apmixedsys_init,
0744 }, {
0745 .compatible = "mediatek,mt7622-infracfg",
0746 .data = mtk_infrasys_init,
0747 }, {
0748 .compatible = "mediatek,mt7622-topckgen",
0749 .data = mtk_topckgen_init,
0750 }, {
0751 .compatible = "mediatek,mt7622-pericfg",
0752 .data = mtk_pericfg_init,
0753 }, {
0754
0755 }
0756 };
0757
0758 static int clk_mt7622_probe(struct platform_device *pdev)
0759 {
0760 int (*clk_init)(struct platform_device *);
0761 int r;
0762
0763 clk_init = of_device_get_match_data(&pdev->dev);
0764 if (!clk_init)
0765 return -EINVAL;
0766
0767 r = clk_init(pdev);
0768 if (r)
0769 dev_err(&pdev->dev,
0770 "could not register clock provider: %s: %d\n",
0771 pdev->name, r);
0772
0773 return r;
0774 }
0775
0776 static struct platform_driver clk_mt7622_drv = {
0777 .probe = clk_mt7622_probe,
0778 .driver = {
0779 .name = "clk-mt7622",
0780 .of_match_table = of_match_clk_mt7622,
0781 },
0782 };
0783
0784 static int clk_mt7622_init(void)
0785 {
0786 return platform_driver_register(&clk_mt7622_drv);
0787 }
0788
0789 arch_initcall(clk_mt7622_init);
