clk/mediatek/clk-mt7622-hif.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2017 MediaTek Inc.
0004  * Author: Chen Zhong <chen.zhong@mediatek.com>
0005  *     Sean Wang <sean.wang@mediatek.com>
0006  */
0007
0008 #include <linux/clk-provider.h>
0009 #include <linux/of.h>
0010 #include <linux/of_address.h>
0011 #include <linux/of_device.h>
0012 #include <linux/platform_device.h>
0013
0014 #include "clk-mtk.h"
0015 #include "clk-gate.h"
0016
0017 #include <dt-bindings/clock/mt7622-clk.h>
0018
0019 #define GATE_PCIE(_id, _name, _parent, _shift) {    \
0020         .id = _id,              \
0021         .name = _name,              \
0022         .parent_name = _parent,         \
0023         .regs = &pcie_cg_regs,          \
0024         .shift = _shift,            \
0025         .ops = &mtk_clk_gate_ops_no_setclr_inv, \
0026     }
0027
0028 #define GATE_SSUSB(_id, _name, _parent, _shift) {   \
0029         .id = _id,              \
0030         .name = _name,              \
0031         .parent_name = _parent,         \
0032         .regs = &ssusb_cg_regs,         \
0033         .shift = _shift,            \
0034         .ops = &mtk_clk_gate_ops_no_setclr_inv, \
0035     }
0036
0037 static const struct mtk_gate_regs pcie_cg_regs = {
0038     .set_ofs = 0x30,
0039     .clr_ofs = 0x30,
0040     .sta_ofs = 0x30,
0041 };
0042
0043 static const struct mtk_gate_regs ssusb_cg_regs = {
0044     .set_ofs = 0x30,
0045     .clr_ofs = 0x30,
0046     .sta_ofs = 0x30,
0047 };
0048
0049 static const struct mtk_gate ssusb_clks[] = {
0050     GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, "ssusb_u2_phy_1p",
0051            "to_u2_phy_1p", 0),
0052     GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, "ssusb_u2_phy_en", "to_u2_phy", 1),
0053     GATE_SSUSB(CLK_SSUSB_REF_EN, "ssusb_ref_en", "to_usb3_ref", 5),
0054     GATE_SSUSB(CLK_SSUSB_SYS_EN, "ssusb_sys_en", "to_usb3_sys", 6),
0055     GATE_SSUSB(CLK_SSUSB_MCU_EN, "ssusb_mcu_en", "axi_sel", 7),
0056     GATE_SSUSB(CLK_SSUSB_DMA_EN, "ssusb_dma_en", "hif_sel", 8),
0057 };
0058
0059 static const struct mtk_gate pcie_clks[] = {
0060     GATE_PCIE(CLK_PCIE_P1_AUX_EN, "pcie_p1_aux_en", "p1_1mhz", 12),
0061     GATE_PCIE(CLK_PCIE_P1_OBFF_EN, "pcie_p1_obff_en", "free_run_4mhz", 13),
0062     GATE_PCIE(CLK_PCIE_P1_AHB_EN, "pcie_p1_ahb_en", "axi_sel", 14),
0063     GATE_PCIE(CLK_PCIE_P1_AXI_EN, "pcie_p1_axi_en", "hif_sel", 15),
0064     GATE_PCIE(CLK_PCIE_P1_MAC_EN, "pcie_p1_mac_en", "pcie1_mac_en", 16),
0065     GATE_PCIE(CLK_PCIE_P1_PIPE_EN, "pcie_p1_pipe_en", "pcie1_pipe_en", 17),
0066     GATE_PCIE(CLK_PCIE_P0_AUX_EN, "pcie_p0_aux_en", "p0_1mhz", 18),
0067     GATE_PCIE(CLK_PCIE_P0_OBFF_EN, "pcie_p0_obff_en", "free_run_4mhz", 19),
0068     GATE_PCIE(CLK_PCIE_P0_AHB_EN, "pcie_p0_ahb_en", "axi_sel", 20),
0069     GATE_PCIE(CLK_PCIE_P0_AXI_EN, "pcie_p0_axi_en", "hif_sel", 21),
0070     GATE_PCIE(CLK_PCIE_P0_MAC_EN, "pcie_p0_mac_en", "pcie0_mac_en", 22),
0071     GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23),
0072     GATE_PCIE(CLK_SATA_AHB_EN, "sata_ahb_en", "axi_sel", 26),
0073     GATE_PCIE(CLK_SATA_AXI_EN, "sata_axi_en", "hif_sel", 27),
0074     GATE_PCIE(CLK_SATA_ASIC_EN, "sata_asic_en", "sata_asic", 28),
0075     GATE_PCIE(CLK_SATA_RBC_EN, "sata_rbc_en", "sata_rbc", 29),
0076     GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en", "univpll2_d4", 30),
0077 };
0078
0079 static u16 rst_ofs[] = { 0x34, };
0080
0081 static const struct mtk_clk_rst_desc clk_rst_desc = {
0082     .version = MTK_RST_SIMPLE,
0083     .rst_bank_ofs = rst_ofs,
0084     .rst_bank_nr = ARRAY_SIZE(rst_ofs),
0085 };
0086
0087 static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
0088 {
0089     struct clk_hw_onecell_data *clk_data;
0090     struct device_node *node = pdev->dev.of_node;
0091     int r;
0092
0093     clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
0094
0095     mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
0096                    clk_data);
0097
0098     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0099     if (r)
0100         dev_err(&pdev->dev,
0101             "could not register clock provider: %s: %d\n",
0102             pdev->name, r);
0103
0104     mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
0105
0106     return r;
0107 }
0108
0109 static int clk_mt7622_pciesys_init(struct platform_device *pdev)
0110 {
0111     struct clk_hw_onecell_data *clk_data;
0112     struct device_node *node = pdev->dev.of_node;
0113     int r;
0114
0115     clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
0116
0117     mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
0118                    clk_data);
0119
0120     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0121     if (r)
0122         dev_err(&pdev->dev,
0123             "could not register clock provider: %s: %d\n",
0124             pdev->name, r);
0125
0126     mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
0127
0128     return r;
0129 }
0130
0131 static const struct of_device_id of_match_clk_mt7622_hif[] = {
0132     {
0133         .compatible = "mediatek,mt7622-pciesys",
0134         .data = clk_mt7622_pciesys_init,
0135     }, {
0136         .compatible = "mediatek,mt7622-ssusbsys",
0137         .data = clk_mt7622_ssusbsys_init,
0138     }, {
0139         /* sentinel */
0140     }
0141 };
0142
0143 static int clk_mt7622_hif_probe(struct platform_device *pdev)
0144 {
0145     int (*clk_init)(struct platform_device *);
0146     int r;
0147
0148     clk_init = of_device_get_match_data(&pdev->dev);
0149     if (!clk_init)
0150         return -EINVAL;
0151
0152     r = clk_init(pdev);
0153     if (r)
0154         dev_err(&pdev->dev,
0155             "could not register clock provider: %s: %d\n",
0156             pdev->name, r);
0157
0158     return r;
0159 }
0160
0161 static struct platform_driver clk_mt7622_hif_drv = {
0162     .probe = clk_mt7622_hif_probe,
0163     .driver = {
0164         .name = "clk-mt7622-hif",
0165         .of_match_table = of_match_clk_mt7622_hif,
0166     },
0167 };
0168
0169 builtin_platform_driver(clk_mt7622_hif_drv);