clk/mediatek/clk-mt7622-aud.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2017 MediaTek Inc.
0004  * Author: Chen Zhong <chen.zhong@mediatek.com>
0005  *     Sean Wang <sean.wang@mediatek.com>
0006  */
0007
0008 #include <linux/clk-provider.h>
0009 #include <linux/of.h>
0010 #include <linux/of_address.h>
0011 #include <linux/of_device.h>
0012 #include <linux/platform_device.h>
0013
0014 #include "clk-mtk.h"
0015 #include "clk-gate.h"
0016
0017 #include <dt-bindings/clock/mt7622-clk.h>
0018
0019 #define GATE_AUDIO0(_id, _name, _parent, _shift) {  \
0020         .id = _id,              \
0021         .name = _name,              \
0022         .parent_name = _parent,         \
0023         .regs = &audio0_cg_regs,            \
0024         .shift = _shift,            \
0025         .ops = &mtk_clk_gate_ops_no_setclr, \
0026     }
0027
0028 #define GATE_AUDIO1(_id, _name, _parent, _shift) {  \
0029         .id = _id,              \
0030         .name = _name,              \
0031         .parent_name = _parent,         \
0032         .regs = &audio1_cg_regs,            \
0033         .shift = _shift,            \
0034         .ops = &mtk_clk_gate_ops_no_setclr, \
0035     }
0036
0037 #define GATE_AUDIO2(_id, _name, _parent, _shift) {  \
0038         .id = _id,              \
0039         .name = _name,              \
0040         .parent_name = _parent,         \
0041         .regs = &audio2_cg_regs,            \
0042         .shift = _shift,            \
0043         .ops = &mtk_clk_gate_ops_no_setclr, \
0044     }
0045
0046 #define GATE_AUDIO3(_id, _name, _parent, _shift) {  \
0047         .id = _id,              \
0048         .name = _name,              \
0049         .parent_name = _parent,         \
0050         .regs = &audio3_cg_regs,            \
0051         .shift = _shift,            \
0052         .ops = &mtk_clk_gate_ops_no_setclr, \
0053     }
0054
0055 static const struct mtk_gate_regs audio0_cg_regs = {
0056     .set_ofs = 0x0,
0057     .clr_ofs = 0x0,
0058     .sta_ofs = 0x0,
0059 };
0060
0061 static const struct mtk_gate_regs audio1_cg_regs = {
0062     .set_ofs = 0x10,
0063     .clr_ofs = 0x10,
0064     .sta_ofs = 0x10,
0065 };
0066
0067 static const struct mtk_gate_regs audio2_cg_regs = {
0068     .set_ofs = 0x14,
0069     .clr_ofs = 0x14,
0070     .sta_ofs = 0x14,
0071 };
0072
0073 static const struct mtk_gate_regs audio3_cg_regs = {
0074     .set_ofs = 0x634,
0075     .clr_ofs = 0x634,
0076     .sta_ofs = 0x634,
0077 };
0078
0079 static const struct mtk_gate audio_clks[] = {
0080     /* AUDIO0 */
0081     GATE_AUDIO0(CLK_AUDIO_AFE, "audio_afe", "rtc", 2),
0082     GATE_AUDIO0(CLK_AUDIO_HDMI, "audio_hdmi", "apll1_ck_sel", 20),
0083     GATE_AUDIO0(CLK_AUDIO_SPDF, "audio_spdf", "apll1_ck_sel", 21),
0084     GATE_AUDIO0(CLK_AUDIO_APLL, "audio_apll", "apll1_ck_sel", 23),
0085     /* AUDIO1 */
0086     GATE_AUDIO1(CLK_AUDIO_I2SIN1, "audio_i2sin1", "a1sys_hp_sel", 0),
0087     GATE_AUDIO1(CLK_AUDIO_I2SIN2, "audio_i2sin2", "a1sys_hp_sel", 1),
0088     GATE_AUDIO1(CLK_AUDIO_I2SIN3, "audio_i2sin3", "a1sys_hp_sel", 2),
0089     GATE_AUDIO1(CLK_AUDIO_I2SIN4, "audio_i2sin4", "a1sys_hp_sel", 3),
0090     GATE_AUDIO1(CLK_AUDIO_I2SO1, "audio_i2so1", "a1sys_hp_sel", 6),
0091     GATE_AUDIO1(CLK_AUDIO_I2SO2, "audio_i2so2", "a1sys_hp_sel", 7),
0092     GATE_AUDIO1(CLK_AUDIO_I2SO3, "audio_i2so3", "a1sys_hp_sel", 8),
0093     GATE_AUDIO1(CLK_AUDIO_I2SO4, "audio_i2so4", "a1sys_hp_sel", 9),
0094     GATE_AUDIO1(CLK_AUDIO_ASRCI1, "audio_asrci1", "asm_h_sel", 12),
0095     GATE_AUDIO1(CLK_AUDIO_ASRCI2, "audio_asrci2", "asm_h_sel", 13),
0096     GATE_AUDIO1(CLK_AUDIO_ASRCO1, "audio_asrco1", "asm_h_sel", 14),
0097     GATE_AUDIO1(CLK_AUDIO_ASRCO2, "audio_asrco2", "asm_h_sel", 15),
0098     GATE_AUDIO1(CLK_AUDIO_INTDIR, "audio_intdir", "intdir_sel", 20),
0099     GATE_AUDIO1(CLK_AUDIO_A1SYS, "audio_a1sys", "a1sys_hp_sel", 21),
0100     GATE_AUDIO1(CLK_AUDIO_A2SYS, "audio_a2sys", "a2sys_hp_sel", 22),
0101     GATE_AUDIO1(CLK_AUDIO_AFE_CONN, "audio_afe_conn", "a1sys_hp_sel", 23),
0102     /* AUDIO2 */
0103     GATE_AUDIO2(CLK_AUDIO_UL1, "audio_ul1", "a1sys_hp_sel", 0),
0104     GATE_AUDIO2(CLK_AUDIO_UL2, "audio_ul2", "a1sys_hp_sel", 1),
0105     GATE_AUDIO2(CLK_AUDIO_UL3, "audio_ul3", "a1sys_hp_sel", 2),
0106     GATE_AUDIO2(CLK_AUDIO_UL4, "audio_ul4", "a1sys_hp_sel", 3),
0107     GATE_AUDIO2(CLK_AUDIO_UL5, "audio_ul5", "a1sys_hp_sel", 4),
0108     GATE_AUDIO2(CLK_AUDIO_UL6, "audio_ul6", "a1sys_hp_sel", 5),
0109     GATE_AUDIO2(CLK_AUDIO_DL1, "audio_dl1", "a1sys_hp_sel", 6),
0110     GATE_AUDIO2(CLK_AUDIO_DL2, "audio_dl2", "a1sys_hp_sel", 7),
0111     GATE_AUDIO2(CLK_AUDIO_DL3, "audio_dl3", "a1sys_hp_sel", 8),
0112     GATE_AUDIO2(CLK_AUDIO_DL4, "audio_dl4", "a1sys_hp_sel", 9),
0113     GATE_AUDIO2(CLK_AUDIO_DL5, "audio_dl5", "a1sys_hp_sel", 10),
0114     GATE_AUDIO2(CLK_AUDIO_DL6, "audio_dl6", "a1sys_hp_sel", 11),
0115     GATE_AUDIO2(CLK_AUDIO_DLMCH, "audio_dlmch", "a1sys_hp_sel", 12),
0116     GATE_AUDIO2(CLK_AUDIO_ARB1, "audio_arb1", "a1sys_hp_sel", 13),
0117     GATE_AUDIO2(CLK_AUDIO_AWB, "audio_awb", "a1sys_hp_sel", 14),
0118     GATE_AUDIO2(CLK_AUDIO_AWB2, "audio_awb2", "a1sys_hp_sel", 15),
0119     GATE_AUDIO2(CLK_AUDIO_DAI, "audio_dai", "a1sys_hp_sel", 16),
0120     GATE_AUDIO2(CLK_AUDIO_MOD, "audio_mod", "a1sys_hp_sel", 17),
0121     /* AUDIO3 */
0122     GATE_AUDIO3(CLK_AUDIO_ASRCI3, "audio_asrci3", "asm_h_sel", 2),
0123     GATE_AUDIO3(CLK_AUDIO_ASRCI4, "audio_asrci4", "asm_h_sel", 3),
0124     GATE_AUDIO3(CLK_AUDIO_ASRCO3, "audio_asrco3", "asm_h_sel", 6),
0125     GATE_AUDIO3(CLK_AUDIO_ASRCO4, "audio_asrco4", "asm_h_sel", 7),
0126     GATE_AUDIO3(CLK_AUDIO_MEM_ASRC1, "audio_mem_asrc1", "asm_h_sel", 10),
0127     GATE_AUDIO3(CLK_AUDIO_MEM_ASRC2, "audio_mem_asrc2", "asm_h_sel", 11),
0128     GATE_AUDIO3(CLK_AUDIO_MEM_ASRC3, "audio_mem_asrc3", "asm_h_sel", 12),
0129     GATE_AUDIO3(CLK_AUDIO_MEM_ASRC4, "audio_mem_asrc4", "asm_h_sel", 13),
0130     GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
0131 };
0132
0133 static int clk_mt7622_audiosys_init(struct platform_device *pdev)
0134 {
0135     struct clk_hw_onecell_data *clk_data;
0136     struct device_node *node = pdev->dev.of_node;
0137     int r;
0138
0139     clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
0140
0141     mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
0142                    clk_data);
0143
0144     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0145     if (r) {
0146         dev_err(&pdev->dev,
0147             "could not register clock provider: %s: %d\n",
0148             pdev->name, r);
0149
0150         goto err_clk_provider;
0151     }
0152
0153     r = devm_of_platform_populate(&pdev->dev);
0154     if (r)
0155         goto err_plat_populate;
0156
0157     return 0;
0158
0159 err_plat_populate:
0160     of_clk_del_provider(node);
0161 err_clk_provider:
0162     return r;
0163 }
0164
0165 static const struct of_device_id of_match_clk_mt7622_aud[] = {
0166     {
0167         .compatible = "mediatek,mt7622-audsys",
0168         .data = clk_mt7622_audiosys_init,
0169     }, {
0170         /* sentinel */
0171     }
0172 };
0173
0174 static int clk_mt7622_aud_probe(struct platform_device *pdev)
0175 {
0176     int (*clk_init)(struct platform_device *);
0177     int r;
0178
0179     clk_init = of_device_get_match_data(&pdev->dev);
0180     if (!clk_init)
0181         return -EINVAL;
0182
0183     r = clk_init(pdev);
0184     if (r)
0185         dev_err(&pdev->dev,
0186             "could not register clock provider: %s: %d\n",
0187             pdev->name, r);
0188
0189     return r;
0190 }
0191
0192 static struct platform_driver clk_mt7622_aud_drv = {
0193     .probe = clk_mt7622_aud_probe,
0194     .driver = {
0195         .name = "clk-mt7622-aud",
0196         .of_match_table = of_match_clk_mt7622_aud,
0197     },
0198 };
0199
0200 builtin_platform_driver(clk_mt7622_aud_drv);