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0007 #include <linux/of.h>
0008 #include <linux/of_address.h>
0009 #include <linux/of_device.h>
0010 #include <linux/platform_device.h>
0011
0012 #include "clk-gate.h"
0013 #include "clk-mtk.h"
0014 #include "clk-pll.h"
0015
0016 #include <dt-bindings/clock/mt6797-clk.h>
0017
0018
0019
0020
0021
0022
0023
0024 static DEFINE_SPINLOCK(mt6797_clk_lock);
0025
0026 static const struct mtk_fixed_factor top_fixed_divs[] = {
0027 FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 1),
0028 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
0029 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
0030 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4),
0031 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),
0032 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
0033 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
0034 FACTOR(CLK_TOP_SYSPLL_D3_D3, "syspll_d3_d3", "syspll_d3", 1, 3),
0035 FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2),
0036 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4),
0037 FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8),
0038 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
0039 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
0040 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4),
0041 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
0042 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
0043 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4),
0044 FACTOR(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1, 1),
0045 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
0046 FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll", 1, 26),
0047 FACTOR(CLK_TOP_SSUSB_PHY_48M_CK, "ssusb_phy_48m_ck", "univpll", 1, 1),
0048 FACTOR(CLK_TOP_USB_PHY48M_CK, "usb_phy48m_ck", "univpll", 1, 1),
0049 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
0050 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
0051 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
0052 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8),
0053 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
0054 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 2),
0055 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 4),
0056 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 8),
0057 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
0058 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2),
0059 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4),
0060 FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8),
0061 FACTOR(CLK_TOP_ULPOSC_CK_ORG, "ulposc_ck_org", "ulposc", 1, 1),
0062 FACTOR(CLK_TOP_ULPOSC_CK, "ulposc_ck", "ulposc_ck_org", 1, 3),
0063 FACTOR(CLK_TOP_ULPOSC_D2, "ulposc_d2", "ulposc_ck", 1, 2),
0064 FACTOR(CLK_TOP_ULPOSC_D3, "ulposc_d3", "ulposc_ck", 1, 4),
0065 FACTOR(CLK_TOP_ULPOSC_D4, "ulposc_d4", "ulposc_ck", 1, 8),
0066 FACTOR(CLK_TOP_ULPOSC_D8, "ulposc_d8", "ulposc_ck", 1, 10),
0067 FACTOR(CLK_TOP_ULPOSC_D10, "ulposc_d10", "ulposc_ck_org", 1, 1),
0068 FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 1),
0069 FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 1),
0070 FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 1),
0071 FACTOR(CLK_TOP_MFGPLL_D2, "mfgpll_d2", "mfgpll_ck", 1, 2),
0072 FACTOR(CLK_TOP_IMGPLL_CK, "imgpll_ck", "imgpll", 1, 1),
0073 FACTOR(CLK_TOP_IMGPLL_D2, "imgpll_d2", "imgpll_ck", 1, 2),
0074 FACTOR(CLK_TOP_IMGPLL_D4, "imgpll_d4", "imgpll_ck", 1, 4),
0075 FACTOR(CLK_TOP_CODECPLL_CK, "codecpll_ck", "codecpll", 1, 1),
0076 FACTOR(CLK_TOP_CODECPLL_D2, "codecpll_d2", "codecpll_ck", 1, 2),
0077 FACTOR(CLK_TOP_VDECPLL_CK, "vdecpll_ck", "vdecpll", 1, 1),
0078 FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 1),
0079 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
0080 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1, 4),
0081 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1, 8),
0082 FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_ck", 1, 16),
0083 FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 1),
0084 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2),
0085 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1, 4),
0086 FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll_ck", 1, 8),
0087 };
0088
0089 static const char * const axi_parents[] = {
0090 "clk26m",
0091 "syspll_d7",
0092 "ulposc_axi_ck_mux",
0093 };
0094
0095 static const char * const ulposc_axi_ck_mux_parents[] = {
0096 "syspll1_d4",
0097 "ulposc_axi_ck_mux_pre",
0098 };
0099
0100 static const char * const ulposc_axi_ck_mux_pre_parents[] = {
0101 "ulposc_d2",
0102 "ulposc_d3",
0103 };
0104
0105 static const char * const ddrphycfg_parents[] = {
0106 "clk26m",
0107 "syspll3_d2",
0108 "syspll2_d4",
0109 "syspll1_d8",
0110 };
0111
0112 static const char * const mm_parents[] = {
0113 "clk26m",
0114 "imgpll_ck",
0115 "univpll1_d2",
0116 "syspll1_d2",
0117 };
0118
0119 static const char * const pwm_parents[] = {
0120 "clk26m",
0121 "univpll2_d4",
0122 "ulposc_d2",
0123 "ulposc_d3",
0124 "ulposc_d8",
0125 "ulposc_d10",
0126 "ulposc_d4",
0127 };
0128
0129 static const char * const vdec_parents[] = {
0130 "clk26m",
0131 "vdecpll_ck",
0132 "imgpll_ck",
0133 "syspll_d3",
0134 "univpll_d5",
0135 "clk26m",
0136 "clk26m",
0137 };
0138
0139 static const char * const venc_parents[] = {
0140 "clk26m",
0141 "codecpll_ck",
0142 "syspll_d3",
0143 };
0144
0145 static const char * const mfg_parents[] = {
0146 "clk26m",
0147 "mfgpll_ck",
0148 "syspll_d3",
0149 "univpll_d3",
0150 };
0151
0152 static const char * const camtg[] = {
0153 "clk26m",
0154 "univpll_d26",
0155 "univpll2_d2",
0156 };
0157
0158 static const char * const uart_parents[] = {
0159 "clk26m",
0160 "univpll2_d8",
0161 };
0162
0163 static const char * const spi_parents[] = {
0164 "clk26m",
0165 "syspll3_d2",
0166 "syspll2_d4",
0167 "ulposc_spi_ck_mux",
0168 };
0169
0170 static const char * const ulposc_spi_ck_mux_parents[] = {
0171 "ulposc_d2",
0172 "ulposc_d3",
0173 };
0174
0175 static const char * const usb20_parents[] = {
0176 "clk26m",
0177 "univpll1_d8",
0178 "syspll4_d2",
0179 };
0180
0181 static const char * const msdc50_0_hclk_parents[] = {
0182 "clk26m",
0183 "syspll1_d2",
0184 "syspll2_d2",
0185 "syspll4_d2",
0186 };
0187
0188 static const char * const msdc50_0_parents[] = {
0189 "clk26m",
0190 "msdcpll",
0191 "syspll_d3",
0192 "univpll1_d4",
0193 "syspll2_d2",
0194 "syspll_d7",
0195 "msdcpll_d2",
0196 "univpll1_d2",
0197 "univpll_d3",
0198 };
0199
0200 static const char * const msdc30_1_parents[] = {
0201 "clk26m",
0202 "univpll2_d2",
0203 "msdcpll_d2",
0204 "univpll1_d4",
0205 "syspll2_d2",
0206 "syspll_d7",
0207 "univpll_d7",
0208 };
0209
0210 static const char * const msdc30_2_parents[] = {
0211 "clk26m",
0212 "univpll2_d8",
0213 "syspll2_d8",
0214 "syspll1_d8",
0215 "msdcpll_d8",
0216 "syspll3_d4",
0217 "univpll_d26",
0218 };
0219
0220 static const char * const audio_parents[] = {
0221 "clk26m",
0222 "syspll3_d4",
0223 "syspll4_d4",
0224 "syspll1_d16",
0225 };
0226
0227 static const char * const aud_intbus_parents[] = {
0228 "clk26m",
0229 "syspll1_d4",
0230 "syspll4_d2",
0231 };
0232
0233 static const char * const pmicspi_parents[] = {
0234 "clk26m",
0235 "univpll_d26",
0236 "syspll3_d4",
0237 "syspll1_d8",
0238 "ulposc_d4",
0239 "ulposc_d8",
0240 "syspll2_d8",
0241 };
0242
0243 static const char * const scp_parents[] = {
0244 "clk26m",
0245 "syspll_d3",
0246 "ulposc_ck",
0247 "univpll_d5",
0248 };
0249
0250 static const char * const atb_parents[] = {
0251 "clk26m",
0252 "syspll1_d2",
0253 "syspll_d5",
0254 };
0255
0256 static const char * const mjc_parents[] = {
0257 "clk26m",
0258 "imgpll_ck",
0259 "univpll_d5",
0260 "syspll1_d2",
0261 };
0262
0263 static const char * const dpi0_parents[] = {
0264 "clk26m",
0265 "tvdpll_d2",
0266 "tvdpll_d4",
0267 "tvdpll_d8",
0268 "tvdpll_d16",
0269 "clk26m",
0270 "clk26m",
0271 };
0272
0273 static const char * const aud_1_parents[] = {
0274 "clk26m",
0275 "apll1_ck",
0276 };
0277
0278 static const char * const aud_2_parents[] = {
0279 "clk26m",
0280 "apll2_ck",
0281 };
0282
0283 static const char * const ssusb_top_sys_parents[] = {
0284 "clk26m",
0285 "univpll3_d2",
0286 };
0287
0288 static const char * const spm_parents[] = {
0289 "clk26m",
0290 "syspll1_d8",
0291 };
0292
0293 static const char * const bsi_spi_parents[] = {
0294 "clk26m",
0295 "syspll_d3_d3",
0296 "syspll1_d4",
0297 "syspll_d7",
0298 };
0299
0300 static const char * const audio_h_parents[] = {
0301 "clk26m",
0302 "apll2_ck",
0303 "apll1_ck",
0304 "univpll_d7",
0305 };
0306
0307 static const char * const mfg_52m_parents[] = {
0308 "clk26m",
0309 "univpll2_d8",
0310 "univpll2_d4",
0311 "univpll2_d4",
0312 };
0313
0314 static const char * const anc_md32_parents[] = {
0315 "clk26m",
0316 "syspll1_d2",
0317 "univpll_d5",
0318 };
0319
0320
0321
0322
0323
0324 static const struct mtk_composite top_muxes[] = {
0325 MUX(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE, "ulposc_axi_ck_mux_pre",
0326 ulposc_axi_ck_mux_pre_parents, 0x0040, 3, 1),
0327 MUX(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX, "ulposc_axi_ck_mux",
0328 ulposc_axi_ck_mux_parents, 0x0040, 2, 1),
0329 MUX(CLK_TOP_MUX_AXI, "axi_sel", axi_parents,
0330 0x0040, 0, 2),
0331 MUX_FLAGS(CLK_TOP_MUX_DDRPHYCFG, "ddrphycfg_sel", ddrphycfg_parents,
0332 0x0040, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
0333 MUX(CLK_TOP_MUX_MM, "mm_sel", mm_parents,
0334 0x0040, 24, 2),
0335 MUX_GATE(CLK_TOP_MUX_PWM, "pwm_sel", pwm_parents, 0x0050, 0, 3, 7),
0336 MUX_GATE(CLK_TOP_MUX_VDEC, "vdec_sel", vdec_parents, 0x0050, 8, 3, 15),
0337 MUX_GATE(CLK_TOP_MUX_VENC, "venc_sel", venc_parents, 0x0050, 16, 2, 23),
0338 MUX_GATE(CLK_TOP_MUX_MFG, "mfg_sel", mfg_parents, 0x0050, 24, 2, 31),
0339 MUX_GATE(CLK_TOP_MUX_CAMTG, "camtg_sel", camtg, 0x0060, 0, 2, 7),
0340 MUX_GATE(CLK_TOP_MUX_UART, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
0341 MUX_GATE(CLK_TOP_MUX_SPI, "spi_sel", spi_parents, 0x0060, 16, 2, 23),
0342 MUX(CLK_TOP_MUX_ULPOSC_SPI_CK_MUX, "ulposc_spi_ck_mux",
0343 ulposc_spi_ck_mux_parents, 0x0060, 18, 1),
0344 MUX_GATE(CLK_TOP_MUX_USB20, "usb20_sel", usb20_parents,
0345 0x0060, 24, 2, 31),
0346 MUX(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_0_hclk_sel",
0347 msdc50_0_hclk_parents, 0x0070, 8, 2),
0348 MUX_GATE(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel", msdc50_0_parents,
0349 0x0070, 16, 4, 23),
0350 MUX_GATE(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel", msdc30_1_parents,
0351 0x0070, 24, 3, 31),
0352 MUX_GATE(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel", msdc30_2_parents,
0353 0x0080, 0, 3, 7),
0354 MUX_GATE(CLK_TOP_MUX_AUDIO, "audio_sel", audio_parents,
0355 0x0080, 16, 2, 23),
0356 MUX(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel", aud_intbus_parents,
0357 0x0080, 24, 2),
0358 MUX(CLK_TOP_MUX_PMICSPI, "pmicspi_sel", pmicspi_parents,
0359 0x0090, 0, 3),
0360 MUX(CLK_TOP_MUX_SCP, "scp_sel", scp_parents,
0361 0x0090, 8, 2),
0362 MUX(CLK_TOP_MUX_ATB, "atb_sel", atb_parents,
0363 0x0090, 16, 2),
0364 MUX_GATE(CLK_TOP_MUX_MJC, "mjc_sel", mjc_parents, 0x0090, 24, 2, 31),
0365 MUX_GATE(CLK_TOP_MUX_DPI0, "dpi0_sel", dpi0_parents, 0x00A0, 0, 3, 7),
0366 MUX_GATE(CLK_TOP_MUX_AUD_1, "aud_1_sel", aud_1_parents,
0367 0x00A0, 16, 1, 23),
0368 MUX_GATE(CLK_TOP_MUX_AUD_2, "aud_2_sel", aud_2_parents,
0369 0x00A0, 24, 1, 31),
0370 MUX(CLK_TOP_MUX_SSUSB_TOP_SYS, "ssusb_top_sys_sel",
0371 ssusb_top_sys_parents, 0x00B0, 8, 1),
0372 MUX(CLK_TOP_MUX_SPM, "spm_sel", spm_parents,
0373 0x00C0, 0, 1),
0374 MUX(CLK_TOP_MUX_BSI_SPI, "bsi_spi_sel", bsi_spi_parents,
0375 0x00C0, 8, 2),
0376 MUX_GATE(CLK_TOP_MUX_AUDIO_H, "audio_h_sel", audio_h_parents,
0377 0x00C0, 16, 2, 23),
0378 MUX_GATE(CLK_TOP_MUX_ANC_MD32, "anc_md32_sel", anc_md32_parents,
0379 0x00C0, 24, 2, 31),
0380 MUX(CLK_TOP_MUX_MFG_52M, "mfg_52m_sel", mfg_52m_parents,
0381 0x0104, 1, 2),
0382 };
0383
0384 static int mtk_topckgen_init(struct platform_device *pdev)
0385 {
0386 struct clk_hw_onecell_data *clk_data;
0387 void __iomem *base;
0388 struct device_node *node = pdev->dev.of_node;
0389
0390 base = devm_platform_ioremap_resource(pdev, 0);
0391 if (IS_ERR(base))
0392 return PTR_ERR(base);
0393
0394 clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
0395
0396 mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),
0397 clk_data);
0398
0399 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
0400 &mt6797_clk_lock, clk_data);
0401
0402 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0403 }
0404
0405 static const struct mtk_gate_regs infra0_cg_regs = {
0406 .set_ofs = 0x0080,
0407 .clr_ofs = 0x0084,
0408 .sta_ofs = 0x0090,
0409 };
0410
0411 static const struct mtk_gate_regs infra1_cg_regs = {
0412 .set_ofs = 0x0088,
0413 .clr_ofs = 0x008c,
0414 .sta_ofs = 0x0094,
0415 };
0416
0417 static const struct mtk_gate_regs infra2_cg_regs = {
0418 .set_ofs = 0x00a8,
0419 .clr_ofs = 0x00ac,
0420 .sta_ofs = 0x00b0,
0421 };
0422
0423 #define GATE_ICG0(_id, _name, _parent, _shift) { \
0424 .id = _id, \
0425 .name = _name, \
0426 .parent_name = _parent, \
0427 .regs = &infra0_cg_regs, \
0428 .shift = _shift, \
0429 .ops = &mtk_clk_gate_ops_setclr, \
0430 }
0431
0432 #define GATE_ICG1(_id, _name, _parent, _shift) \
0433 GATE_ICG1_FLAGS(_id, _name, _parent, _shift, 0)
0434
0435 #define GATE_ICG1_FLAGS(_id, _name, _parent, _shift, _flags) { \
0436 .id = _id, \
0437 .name = _name, \
0438 .parent_name = _parent, \
0439 .regs = &infra1_cg_regs, \
0440 .shift = _shift, \
0441 .ops = &mtk_clk_gate_ops_setclr, \
0442 .flags = _flags, \
0443 }
0444
0445 #define GATE_ICG2(_id, _name, _parent, _shift) \
0446 GATE_ICG2_FLAGS(_id, _name, _parent, _shift, 0)
0447
0448 #define GATE_ICG2_FLAGS(_id, _name, _parent, _shift, _flags) { \
0449 .id = _id, \
0450 .name = _name, \
0451 .parent_name = _parent, \
0452 .regs = &infra2_cg_regs, \
0453 .shift = _shift, \
0454 .ops = &mtk_clk_gate_ops_setclr, \
0455 .flags = _flags, \
0456 }
0457
0458
0459
0460
0461
0462 static const struct mtk_gate infra_clks[] = {
0463 GATE_ICG0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "ulposc", 0),
0464 GATE_ICG0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "pmicspi_sel", 1),
0465 GATE_ICG0(CLK_INFRA_PMIC_MD, "infra_pmic_md", "pmicspi_sel", 2),
0466 GATE_ICG0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", "pmicspi_sel", 3),
0467 GATE_ICG0(CLK_INFRA_SCP, "infra_scp", "scp_sel", 4),
0468 GATE_ICG0(CLK_INFRA_SEJ, "infra_sej", "axi_sel", 5),
0469 GATE_ICG0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6),
0470 GATE_ICG0(CLK_INFRA_SEJ_13M, "infra_sej_13m", "clk26m", 7),
0471 GATE_ICG0(CLK_INFRA_ICUSB, "infra_icusb", "usb20_sel", 8),
0472 GATE_ICG0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 9),
0473 GATE_ICG0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10),
0474 GATE_ICG0(CLK_INFRA_I2C0, "infra_i2c0", "axi_sel", 11),
0475 GATE_ICG0(CLK_INFRA_I2C1, "infra_i2c1", "axi_sel", 12),
0476 GATE_ICG0(CLK_INFRA_I2C2, "infra_i2c2", "axi_sel", 13),
0477 GATE_ICG0(CLK_INFRA_I2C3, "infra_i2c3", "axi_sel", 14),
0478 GATE_ICG0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk", "axi_sel", 15),
0479 GATE_ICG0(CLK_INFRA_PWM1, "infra_pwm1", "axi_sel", 16),
0480 GATE_ICG0(CLK_INFRA_PWM2, "infra_pwm2", "axi_sel", 17),
0481 GATE_ICG0(CLK_INFRA_PWM3, "infra_pwm3", "axi_sel", 18),
0482 GATE_ICG0(CLK_INFRA_PWM4, "infra_pwm4", "axi_sel", 19),
0483 GATE_ICG0(CLK_INFRA_PWM, "infra_pwm", "axi_sel", 21),
0484 GATE_ICG0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22),
0485 GATE_ICG0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23),
0486 GATE_ICG0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24),
0487 GATE_ICG0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25),
0488 GATE_ICG0(CLK_INFRA_MD2MD_CCIF_0, "infra_md2md_ccif_0", "axi_sel", 27),
0489 GATE_ICG0(CLK_INFRA_MD2MD_CCIF_1, "infra_md2md_ccif_1", "axi_sel", 28),
0490 GATE_ICG0(CLK_INFRA_MD2MD_CCIF_2, "infra_md2md_ccif_2", "axi_sel", 29),
0491 GATE_ICG0(CLK_INFRA_FHCTL, "infra_fhctl", "clk26m", 30),
0492 GATE_ICG0(CLK_INFRA_BTIF, "infra_btif", "axi_sel", 31),
0493 GATE_ICG1(CLK_INFRA_MD2MD_CCIF_3, "infra_md2md_ccif_3", "axi_sel", 0),
0494 GATE_ICG1(CLK_INFRA_SPI, "infra_spi", "spi_sel", 1),
0495 GATE_ICG1(CLK_INFRA_MSDC0, "infra_msdc0", "msdc50_0_sel", 2),
0496 GATE_ICG1(CLK_INFRA_MD2MD_CCIF_4, "infra_md2md_ccif_4", "axi_sel", 3),
0497 GATE_ICG1(CLK_INFRA_MSDC1, "infra_msdc1", "msdc30_1_sel", 4),
0498 GATE_ICG1(CLK_INFRA_MSDC2, "infra_msdc2", "msdc30_2_sel", 5),
0499 GATE_ICG1(CLK_INFRA_MD2MD_CCIF_5, "infra_md2md_ccif_5", "axi_sel", 7),
0500 GATE_ICG1(CLK_INFRA_GCPU, "infra_gcpu", "axi_sel", 8),
0501 GATE_ICG1(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 9),
0502 GATE_ICG1(CLK_INFRA_AUXADC, "infra_auxadc", "clk26m", 10),
0503 GATE_ICG1(CLK_INFRA_CPUM, "infra_cpum", "axi_sel", 11),
0504 GATE_ICG1(CLK_INFRA_AP_C2K_CCIF_0, "infra_ap_c2k_ccif_0",
0505 "axi_sel", 12),
0506 GATE_ICG1(CLK_INFRA_AP_C2K_CCIF_1, "infra_ap_c2k_ccif_1",
0507 "axi_sel", 13),
0508 GATE_ICG1(CLK_INFRA_CLDMA, "infra_cldma", "axi_sel", 16),
0509 GATE_ICG1(CLK_INFRA_DISP_PWM, "infra_disp_pwm", "pwm_sel", 17),
0510 GATE_ICG1(CLK_INFRA_AP_DMA, "infra_ap_dma", "axi_sel", 18),
0511 GATE_ICG1(CLK_INFRA_DEVICE_APC, "infra_device_apc", "axi_sel", 20),
0512 GATE_ICG1(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "mm_sel", 22),
0513 GATE_ICG1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23),
0514 GATE_ICG1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25),
0515 GATE_ICG1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26),
0516 GATE_ICG1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
0517 "clk26m", 31, CLK_IS_CRITICAL),
0518 GATE_ICG2(CLK_INFRA_I2C4, "infra_i2c4", "axi_sel", 0),
0519 GATE_ICG2(CLK_INFRA_I2C_APPM, "infra_i2c_appm", "axi_sel", 1),
0520 GATE_ICG2(CLK_INFRA_I2C_GPUPM, "infra_i2c_gpupm", "axi_sel", 2),
0521 GATE_ICG2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", "axi_sel", 3),
0522 GATE_ICG2(CLK_INFRA_I2C2_ARB, "infra_i2c2_arb", "axi_sel", 4),
0523 GATE_ICG2(CLK_INFRA_I2C3_IMM, "infra_i2c3_imm", "axi_sel", 5),
0524 GATE_ICG2(CLK_INFRA_I2C3_ARB, "infra_i2c3_arb", "axi_sel", 6),
0525 GATE_ICG2(CLK_INFRA_I2C5, "infra_i2c5", "axi_sel", 7),
0526 GATE_ICG2(CLK_INFRA_SYS_CIRQ, "infra_sys_cirq", "axi_sel", 8),
0527 GATE_ICG2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 10),
0528 GATE_ICG2_FLAGS(CLK_INFRA_DRAMC_B_F26M, "infra_dramc_b_f26m",
0529 "clk26m", 11, CLK_IS_CRITICAL),
0530 GATE_ICG2(CLK_INFRA_ANC_MD32, "infra_anc_md32", "anc_md32_sel", 12),
0531 GATE_ICG2(CLK_INFRA_ANC_MD32_32K, "infra_anc_md32_32k", "clk26m", 13),
0532 GATE_ICG2(CLK_INFRA_DVFS_SPM1, "infra_dvfs_spm1", "axi_sel", 15),
0533 GATE_ICG2(CLK_INFRA_AES_TOP0, "infra_aes_top0", "axi_sel", 16),
0534 GATE_ICG2(CLK_INFRA_AES_TOP1, "infra_aes_top1", "axi_sel", 17),
0535 GATE_ICG2(CLK_INFRA_SSUSB_BUS, "infra_ssusb_bus", "axi_sel", 18),
0536 GATE_ICG2(CLK_INFRA_SPI2, "infra_spi2", "spi_sel", 19),
0537 GATE_ICG2(CLK_INFRA_SPI3, "infra_spi3", "spi_sel", 20),
0538 GATE_ICG2(CLK_INFRA_SPI4, "infra_spi4", "spi_sel", 21),
0539 GATE_ICG2(CLK_INFRA_SPI5, "infra_spi5", "spi_sel", 22),
0540 GATE_ICG2(CLK_INFRA_IRTX, "infra_irtx", "spi_sel", 23),
0541 GATE_ICG2(CLK_INFRA_SSUSB_SYS, "infra_ssusb_sys",
0542 "ssusb_top_sys_sel", 24),
0543 GATE_ICG2(CLK_INFRA_SSUSB_REF, "infra_ssusb_ref", "clk26m", 9),
0544 GATE_ICG2(CLK_INFRA_AUDIO_26M, "infra_audio_26m", "clk26m", 26),
0545 GATE_ICG2(CLK_INFRA_AUDIO_26M_PAD_TOP, "infra_audio_26m_pad_top",
0546 "clk26m", 27),
0547 GATE_ICG2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_modem_temp_share",
0548 "axi_sel", 28),
0549 GATE_ICG2(CLK_INFRA_VAD_WRAP_SOC, "infra_vad_wrap_soc", "axi_sel", 29),
0550 GATE_ICG2(CLK_INFRA_DRAMC_CONF, "infra_dramc_conf", "axi_sel", 30),
0551 GATE_ICG2(CLK_INFRA_DRAMC_B_CONF, "infra_dramc_b_conf", "axi_sel", 31),
0552 GATE_ICG1(CLK_INFRA_MFG_VCG, "infra_mfg_vcg", "mfg_52m_sel", 14),
0553 };
0554
0555 static const struct mtk_fixed_factor infra_fixed_divs[] = {
0556 FACTOR(CLK_INFRA_13M, "clk13m", "clk26m", 1, 2),
0557 };
0558
0559 static struct clk_hw_onecell_data *infra_clk_data;
0560
0561 static void mtk_infrasys_init_early(struct device_node *node)
0562 {
0563 int r, i;
0564
0565 if (!infra_clk_data) {
0566 infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
0567
0568 for (i = 0; i < CLK_INFRA_NR; i++)
0569 infra_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
0570 }
0571
0572 mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
0573 infra_clk_data);
0574
0575 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
0576 infra_clk_data);
0577 if (r)
0578 pr_err("%s(): could not register clock provider: %d\n",
0579 __func__, r);
0580 }
0581
0582 CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt6797-infracfg",
0583 mtk_infrasys_init_early);
0584
0585 static int mtk_infrasys_init(struct platform_device *pdev)
0586 {
0587 int i;
0588 struct device_node *node = pdev->dev.of_node;
0589
0590 if (!infra_clk_data) {
0591 infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
0592 } else {
0593 for (i = 0; i < CLK_INFRA_NR; i++) {
0594 if (infra_clk_data->hws[i] == ERR_PTR(-EPROBE_DEFER))
0595 infra_clk_data->hws[i] = ERR_PTR(-ENOENT);
0596 }
0597 }
0598
0599 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
0600 infra_clk_data);
0601 mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
0602 infra_clk_data);
0603
0604 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
0605 infra_clk_data);
0606 }
0607
0608 #define MT6797_PLL_FMAX (3000UL * MHZ)
0609
0610 #define CON0_MT6797_RST_BAR BIT(24)
0611
0612 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
0613 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
0614 _pcw_shift, _div_table) { \
0615 .id = _id, \
0616 .name = _name, \
0617 .reg = _reg, \
0618 .pwr_reg = _pwr_reg, \
0619 .en_mask = _en_mask, \
0620 .flags = _flags, \
0621 .rst_bar_mask = CON0_MT6797_RST_BAR, \
0622 .fmax = MT6797_PLL_FMAX, \
0623 .pcwbits = _pcwbits, \
0624 .pd_reg = _pd_reg, \
0625 .pd_shift = _pd_shift, \
0626 .tuner_reg = _tuner_reg, \
0627 .pcw_reg = _pcw_reg, \
0628 .pcw_shift = _pcw_shift, \
0629 .div_table = _div_table, \
0630 }
0631
0632 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
0633 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
0634 _pcw_shift) \
0635 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
0636 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
0637 NULL)
0638
0639 static const struct mtk_pll_data plls[] = {
0640 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0xF0000100, PLL_AO,
0641 21, 0x220, 4, 0x0, 0x224, 0),
0642 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0230, 0x023C, 0xFE000010, 0, 7,
0643 0x230, 4, 0x0, 0x234, 14),
0644 PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000100, 0, 21,
0645 0x244, 24, 0x0, 0x244, 0),
0646 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000120, 0, 21,
0647 0x250, 4, 0x0, 0x254, 0),
0648 PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0260, 0x026C, 0x00000120, 0, 21,
0649 0x260, 4, 0x0, 0x264, 0),
0650 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0xC0000120, 0, 21,
0651 0x270, 4, 0x0, 0x274, 0),
0652 PLL(CLK_APMIXED_CODECPLL, "codecpll", 0x0290, 0x029C, 0x00000120, 0, 21,
0653 0x290, 4, 0x0, 0x294, 0),
0654 PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x02E4, 0x02F0, 0x00000120, 0, 21,
0655 0x2E4, 4, 0x0, 0x2E8, 0),
0656 PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000130, 0, 31,
0657 0x2A0, 4, 0x2A8, 0x2A4, 0),
0658 PLL(CLK_APMIXED_APLL2, "apll2", 0x02B4, 0x02C4, 0x00000130, 0, 31,
0659 0x2B4, 4, 0x2BC, 0x2B8, 0),
0660 };
0661
0662 static int mtk_apmixedsys_init(struct platform_device *pdev)
0663 {
0664 struct clk_hw_onecell_data *clk_data;
0665 struct device_node *node = pdev->dev.of_node;
0666
0667 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR);
0668 if (!clk_data)
0669 return -ENOMEM;
0670
0671 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
0672
0673 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0674 }
0675
0676 static const struct of_device_id of_match_clk_mt6797[] = {
0677 {
0678 .compatible = "mediatek,mt6797-topckgen",
0679 .data = mtk_topckgen_init,
0680 }, {
0681 .compatible = "mediatek,mt6797-infracfg",
0682 .data = mtk_infrasys_init,
0683 }, {
0684 .compatible = "mediatek,mt6797-apmixedsys",
0685 .data = mtk_apmixedsys_init,
0686 }, {
0687
0688 }
0689 };
0690
0691 static int clk_mt6797_probe(struct platform_device *pdev)
0692 {
0693 int (*clk_init)(struct platform_device *);
0694 int r;
0695
0696 clk_init = of_device_get_match_data(&pdev->dev);
0697 if (!clk_init)
0698 return -EINVAL;
0699
0700 r = clk_init(pdev);
0701 if (r)
0702 dev_err(&pdev->dev,
0703 "could not register clock provider: %s: %d\n",
0704 pdev->name, r);
0705
0706 return r;
0707 }
0708
0709 static struct platform_driver clk_mt6797_drv = {
0710 .probe = clk_mt6797_probe,
0711 .driver = {
0712 .name = "clk-mt6797",
0713 .of_match_table = of_match_clk_mt6797,
0714 },
0715 };
0716
0717 static int __init clk_mt6797_init(void)
0718 {
0719 return platform_driver_register(&clk_mt6797_drv);
0720 }
0721
0722 arch_initcall(clk_mt6797_init);
