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0007 #include <linux/clk-provider.h>
0008 #include <linux/platform_device.h>
0009
0010 #include "clk-mtk.h"
0011 #include "clk-gate.h"
0012
0013 #include <dt-bindings/clock/mt6797-clk.h>
0014
0015 static const struct mtk_gate_regs venc_cg_regs = {
0016 .set_ofs = 0x0004,
0017 .clr_ofs = 0x0008,
0018 .sta_ofs = 0x0000,
0019 };
0020
0021 #define GATE_VENC(_id, _name, _parent, _shift) { \
0022 .id = _id, \
0023 .name = _name, \
0024 .parent_name = _parent, \
0025 .regs = &venc_cg_regs, \
0026 .shift = _shift, \
0027 .ops = &mtk_clk_gate_ops_setclr_inv, \
0028 }
0029
0030 static const struct mtk_gate venc_clks[] = {
0031 GATE_VENC(CLK_VENC_0, "venc_0", "mm_sel", 0),
0032 GATE_VENC(CLK_VENC_1, "venc_1", "venc_sel", 4),
0033 GATE_VENC(CLK_VENC_2, "venc_2", "venc_sel", 8),
0034 GATE_VENC(CLK_VENC_3, "venc_3", "venc_sel", 12),
0035 };
0036
0037 static const struct of_device_id of_match_clk_mt6797_venc[] = {
0038 { .compatible = "mediatek,mt6797-vencsys", },
0039 {}
0040 };
0041
0042 static int clk_mt6797_venc_probe(struct platform_device *pdev)
0043 {
0044 struct clk_hw_onecell_data *clk_data;
0045 int r;
0046 struct device_node *node = pdev->dev.of_node;
0047
0048 clk_data = mtk_alloc_clk_data(CLK_VENC_NR);
0049
0050 mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
0051 clk_data);
0052
0053 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0054 if (r)
0055 dev_err(&pdev->dev,
0056 "could not register clock provider: %s: %d\n",
0057 pdev->name, r);
0058
0059 return r;
0060 }
0061
0062 static struct platform_driver clk_mt6797_venc_drv = {
0063 .probe = clk_mt6797_venc_probe,
0064 .driver = {
0065 .name = "clk-mt6797-venc",
0066 .of_match_table = of_match_clk_mt6797_venc,
0067 },
0068 };
0069
0070 builtin_platform_driver(clk_mt6797_venc_drv);