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0006 #include <linux/clk-provider.h>
0007 #include <linux/platform_device.h>
0008 #include <dt-bindings/clock/mt6797-clk.h>
0009
0010 #include "clk-mtk.h"
0011 #include "clk-gate.h"
0012
0013 static const struct mtk_gate_regs img_cg_regs = {
0014 .set_ofs = 0x0004,
0015 .clr_ofs = 0x0008,
0016 .sta_ofs = 0x0000,
0017 };
0018
0019 #define GATE_IMG(_id, _name, _parent, _shift) { \
0020 .id = _id, \
0021 .name = _name, \
0022 .parent_name = _parent, \
0023 .regs = &img_cg_regs, \
0024 .shift = _shift, \
0025 .ops = &mtk_clk_gate_ops_setclr, \
0026 }
0027
0028 static const struct mtk_gate img_clks[] = {
0029 GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "mm_sel", 11),
0030 GATE_IMG(CLK_IMG_DPE, "img_dpe", "mm_sel", 10),
0031 GATE_IMG(CLK_IMG_DIP, "img_dip", "mm_sel", 6),
0032 GATE_IMG(CLK_IMG_LARB6, "img_larb6", "mm_sel", 0),
0033 };
0034
0035 static const struct of_device_id of_match_clk_mt6797_img[] = {
0036 { .compatible = "mediatek,mt6797-imgsys", },
0037 {}
0038 };
0039
0040 static int clk_mt6797_img_probe(struct platform_device *pdev)
0041 {
0042 struct clk_hw_onecell_data *clk_data;
0043 int r;
0044 struct device_node *node = pdev->dev.of_node;
0045
0046 clk_data = mtk_alloc_clk_data(CLK_IMG_NR);
0047
0048 mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
0049 clk_data);
0050
0051 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0052 if (r)
0053 dev_err(&pdev->dev,
0054 "could not register clock provider: %s: %d\n",
0055 pdev->name, r);
0056
0057 return r;
0058 }
0059
0060 static struct platform_driver clk_mt6797_img_drv = {
0061 .probe = clk_mt6797_img_probe,
0062 .driver = {
0063 .name = "clk-mt6797-img",
0064 .of_match_table = of_match_clk_mt6797_img,
0065 },
0066 };
0067
0068 builtin_platform_driver(clk_mt6797_img_drv);