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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2019 MediaTek Inc.
0004  * Author: Wendell Lin <wendell.lin@mediatek.com>
0005  */
0006 
0007 #include <linux/module.h>
0008 #include <linux/of.h>
0009 #include <linux/of_address.h>
0010 #include <linux/of_device.h>
0011 #include <linux/platform_device.h>
0012 
0013 #include "clk-gate.h"
0014 #include "clk-mtk.h"
0015 #include "clk-mux.h"
0016 #include "clk-pll.h"
0017 
0018 #include <dt-bindings/clock/mt6779-clk.h>
0019 
0020 static DEFINE_SPINLOCK(mt6779_clk_lock);
0021 
0022 static const struct mtk_fixed_clk top_fixed_clks[] = {
0023     FIXED_CLK(CLK_TOP_CLK26M, "f_f26m_ck", "clk26m", 26000000),
0024 };
0025 
0026 static const struct mtk_fixed_factor top_divs[] = {
0027     FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1, 2),
0028     FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1, 2),
0029     FACTOR(CLK_TOP_MAINPLL_CK, "mainpll_ck", "mainpll", 1, 1),
0030     FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll_ck", 1, 2),
0031     FACTOR(CLK_TOP_MAINPLL_D2_D2, "mainpll_d2_d2", "mainpll_d2", 1, 2),
0032     FACTOR(CLK_TOP_MAINPLL_D2_D4, "mainpll_d2_d4", "mainpll_d2", 1, 4),
0033     FACTOR(CLK_TOP_MAINPLL_D2_D8, "mainpll_d2_d8", "mainpll_d2", 1, 8),
0034     FACTOR(CLK_TOP_MAINPLL_D2_D16, "mainpll_d2_d16", "mainpll_d2", 1, 16),
0035     FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
0036     FACTOR(CLK_TOP_MAINPLL_D3_D2, "mainpll_d3_d2", "mainpll_d3", 1, 2),
0037     FACTOR(CLK_TOP_MAINPLL_D3_D4, "mainpll_d3_d4", "mainpll_d3", 1, 4),
0038     FACTOR(CLK_TOP_MAINPLL_D3_D8, "mainpll_d3_d8", "mainpll_d3", 1, 8),
0039     FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
0040     FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2),
0041     FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4),
0042     FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
0043     FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2),
0044     FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4),
0045     FACTOR(CLK_TOP_UNIVPLL_CK, "univpll", "univ2pll", 1, 2),
0046     FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
0047     FACTOR(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 2),
0048     FACTOR(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 4),
0049     FACTOR(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1, 8),
0050     FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
0051     FACTOR(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 2),
0052     FACTOR(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 4),
0053     FACTOR(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 8),
0054     FACTOR(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1, 16),
0055     FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
0056     FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2),
0057     FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
0058     FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8),
0059     FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
0060     FACTOR(CLK_TOP_UNIVP_192M_CK, "univpll_192m_ck", "univ2pll", 1, 13),
0061     FACTOR(CLK_TOP_UNIVP_192M_D2, "univpll_192m_d2", "univpll_192m_ck",
0062            1, 2),
0063     FACTOR(CLK_TOP_UNIVP_192M_D4, "univpll_192m_d4", "univpll_192m_ck",
0064            1, 4),
0065     FACTOR(CLK_TOP_UNIVP_192M_D8, "univpll_192m_d8", "univpll_192m_ck",
0066            1, 8),
0067     FACTOR(CLK_TOP_UNIVP_192M_D16, "univpll_192m_d16", "univpll_192m_ck",
0068            1, 16),
0069     FACTOR(CLK_TOP_UNIVP_192M_D32, "univpll_192m_d32", "univpll_192m_ck",
0070            1, 32),
0071     FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 1),
0072     FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2),
0073     FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
0074     FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8),
0075     FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 1),
0076     FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
0077     FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
0078     FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8),
0079     FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 1),
0080     FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
0081     FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
0082     FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8),
0083     FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16),
0084     FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1, 1),
0085     FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
0086     FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2),
0087     FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 4),
0088     FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
0089     FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2),
0090     FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4),
0091     FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6),
0092     FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
0093     FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 1),
0094     FACTOR(CLK_TOP_ADSPPLL_CK, "adsppll_ck", "adsppll", 1, 1),
0095     FACTOR(CLK_TOP_ADSPPLL_D4, "adsppll_d4", "adsppll", 1, 4),
0096     FACTOR(CLK_TOP_ADSPPLL_D5, "adsppll_d5", "adsppll", 1, 5),
0097     FACTOR(CLK_TOP_ADSPPLL_D6, "adsppll_d6", "adsppll", 1, 6),
0098     FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 1),
0099     FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
0100     FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
0101     FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8),
0102     FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16),
0103     FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1, 1),
0104     FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1, 2),
0105     FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1, 4),
0106     FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1, 8),
0107     FACTOR(CLK_TOP_OSC_D10, "osc_d10", "osc", 1, 10),
0108     FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1, 16),
0109     FACTOR(CLK_TOP_AD_OSC2_CK, "ad_osc2_ck", "osc2", 1, 1),
0110     FACTOR(CLK_TOP_OSC2_D2, "osc2_d2", "osc2", 1, 2),
0111     FACTOR(CLK_TOP_OSC2_D3, "osc2_d3", "osc2", 1, 3),
0112     FACTOR(CLK_TOP_TVDPLL_MAINPLL_D2_CK, "tvdpll_mainpll_d2_ck",
0113            "tvdpll", 1, 1),
0114     FACTOR(CLK_TOP_FMEM_466M_CK, "fmem_466m_ck", "fmem", 1, 1),
0115 };
0116 
0117 static const char * const axi_parents[] = {
0118     "clk26m",
0119     "mainpll_d2_d4",
0120     "mainpll_d7",
0121     "osc_d4"
0122 };
0123 
0124 static const char * const mm_parents[] = {
0125     "clk26m",
0126     "tvdpll_mainpll_d2_ck",
0127     "mmpll_d7",
0128     "mmpll_d5_d2",
0129     "mainpll_d2_d2",
0130     "mainpll_d3_d2"
0131 };
0132 
0133 static const char * const scp_parents[] = {
0134     "clk26m",
0135     "univpll_d2_d8",
0136     "mainpll_d2_d4",
0137     "mainpll_d3",
0138     "univpll_d3",
0139     "ad_osc2_ck",
0140     "osc2_d2",
0141     "osc2_d3"
0142 };
0143 
0144 static const char * const img_parents[] = {
0145     "clk26m",
0146     "mainpll_d2",
0147     "mainpll_d2",
0148     "univpll_d3",
0149     "mainpll_d3",
0150     "mmpll_d5_d2",
0151     "tvdpll_mainpll_d2_ck",
0152     "mainpll_d5"
0153 };
0154 
0155 static const char * const ipe_parents[] = {
0156     "clk26m",
0157     "mainpll_d2",
0158     "mmpll_d7",
0159     "univpll_d3",
0160     "mainpll_d3",
0161     "mmpll_d5_d2",
0162     "mainpll_d2_d2",
0163     "mainpll_d5"
0164 };
0165 
0166 static const char * const dpe_parents[] = {
0167     "clk26m",
0168     "mainpll_d2",
0169     "mmpll_d7",
0170     "univpll_d3",
0171     "mainpll_d3",
0172     "mmpll_d5_d2",
0173     "mainpll_d2_d2",
0174     "mainpll_d5"
0175 };
0176 
0177 static const char * const cam_parents[] = {
0178     "clk26m",
0179     "mainpll_d2",
0180     "mmpll_d6",
0181     "mainpll_d3",
0182     "mmpll_d7",
0183     "univpll_d3",
0184     "mmpll_d5_d2",
0185     "adsppll_d5",
0186     "tvdpll_mainpll_d2_ck",
0187     "univpll_d3_d2"
0188 };
0189 
0190 static const char * const ccu_parents[] = {
0191     "clk26m",
0192     "mainpll_d2",
0193     "mmpll_d6",
0194     "mainpll_d3",
0195     "mmpll_d7",
0196     "univpll_d3",
0197     "mmpll_d5_d2",
0198     "mainpll_d2_d2",
0199     "adsppll_d5",
0200     "univpll_d3_d2"
0201 };
0202 
0203 static const char * const dsp_parents[] = {
0204     "clk26m",
0205     "univpll_d3_d8",
0206     "univpll_d3_d4",
0207     "mainpll_d2_d4",
0208     "univpll_d3_d2",
0209     "mainpll_d2_d2",
0210     "univpll_d2_d2",
0211     "mainpll_d3",
0212     "univpll_d3",
0213     "mmpll_d7",
0214     "mmpll_d6",
0215     "adsppll_d5",
0216     "tvdpll_ck",
0217     "tvdpll_mainpll_d2_ck",
0218     "univpll_d2",
0219     "adsppll_d4"
0220 };
0221 
0222 static const char * const dsp1_parents[] = {
0223     "clk26m",
0224     "univpll_d3_d8",
0225     "univpll_d3_d4",
0226     "mainpll_d2_d4",
0227     "univpll_d3_d2",
0228     "mainpll_d2_d2",
0229     "univpll_d2_d2",
0230     "mainpll_d3",
0231     "univpll_d3",
0232     "mmpll_d7",
0233     "mmpll_d6",
0234     "adsppll_d5",
0235     "tvdpll_ck",
0236     "tvdpll_mainpll_d2_ck",
0237     "univpll_d2",
0238     "adsppll_d4"
0239 };
0240 
0241 static const char * const dsp2_parents[] = {
0242     "clk26m",
0243     "univpll_d3_d8",
0244     "univpll_d3_d4",
0245     "mainpll_d2_d4",
0246     "univpll_d3_d2",
0247     "mainpll_d2_d2",
0248     "univpll_d2_d2",
0249     "mainpll_d3",
0250     "univpll_d3",
0251     "mmpll_d7",
0252     "mmpll_d6",
0253     "adsppll_d5",
0254     "tvdpll_ck",
0255     "tvdpll_mainpll_d2_ck",
0256     "univpll_d2",
0257     "adsppll_d4"
0258 };
0259 
0260 static const char * const dsp3_parents[] = {
0261     "clk26m",
0262     "univpll_d3_d8",
0263     "mainpll_d2_d4",
0264     "univpll_d3_d2",
0265     "mainpll_d2_d2",
0266     "univpll_d2_d2",
0267     "mainpll_d3",
0268     "univpll_d3",
0269     "mmpll_d7",
0270     "mmpll_d6",
0271     "mainpll_d2",
0272     "tvdpll_ck",
0273     "tvdpll_mainpll_d2_ck",
0274     "univpll_d2",
0275     "adsppll_d4",
0276     "mmpll_d4"
0277 };
0278 
0279 static const char * const ipu_if_parents[] = {
0280     "clk26m",
0281     "univpll_d3_d8",
0282     "univpll_d3_d4",
0283     "mainpll_d2_d4",
0284     "univpll_d3_d2",
0285     "mainpll_d2_d2",
0286     "univpll_d2_d2",
0287     "mainpll_d3",
0288     "univpll_d3",
0289     "mmpll_d7",
0290     "mmpll_d6",
0291     "adsppll_d5",
0292     "tvdpll_ck",
0293     "tvdpll_mainpll_d2_ck",
0294     "univpll_d2",
0295     "adsppll_d4"
0296 };
0297 
0298 static const char * const mfg_parents[] = {
0299     "clk26m",
0300     "mfgpll_ck",
0301     "univpll_d3",
0302     "mainpll_d5"
0303 };
0304 
0305 static const char * const f52m_mfg_parents[] = {
0306     "clk26m",
0307     "univpll_d3_d2",
0308     "univpll_d3_d4",
0309     "univpll_d3_d8"
0310 };
0311 
0312 static const char * const camtg_parents[] = {
0313     "clk26m",
0314     "univpll_192m_d8",
0315     "univpll_d3_d8",
0316     "univpll_192m_d4",
0317     "univpll_d3_d16",
0318     "csw_f26m_ck_d2",
0319     "univpll_192m_d16",
0320     "univpll_192m_d32"
0321 };
0322 
0323 static const char * const camtg2_parents[] = {
0324     "clk26m",
0325     "univpll_192m_d8",
0326     "univpll_d3_d8",
0327     "univpll_192m_d4",
0328     "univpll_d3_d16",
0329     "csw_f26m_ck_d2",
0330     "univpll_192m_d16",
0331     "univpll_192m_d32"
0332 };
0333 
0334 static const char * const camtg3_parents[] = {
0335     "clk26m",
0336     "univpll_192m_d8",
0337     "univpll_d3_d8",
0338     "univpll_192m_d4",
0339     "univpll_d3_d16",
0340     "csw_f26m_ck_d2",
0341     "univpll_192m_d16",
0342     "univpll_192m_d32"
0343 };
0344 
0345 static const char * const camtg4_parents[] = {
0346     "clk26m",
0347     "univpll_192m_d8",
0348     "univpll_d3_d8",
0349     "univpll_192m_d4",
0350     "univpll_d3_d16",
0351     "csw_f26m_ck_d2",
0352     "univpll_192m_d16",
0353     "univpll_192m_d32"
0354 };
0355 
0356 static const char * const uart_parents[] = {
0357     "clk26m",
0358     "univpll_d3_d8"
0359 };
0360 
0361 static const char * const spi_parents[] = {
0362     "clk26m",
0363     "mainpll_d5_d2",
0364     "mainpll_d3_d4",
0365     "msdcpll_d4"
0366 };
0367 
0368 static const char * const msdc50_hclk_parents[] = {
0369     "clk26m",
0370     "mainpll_d2_d2",
0371     "mainpll_d3_d2"
0372 };
0373 
0374 static const char * const msdc50_0_parents[] = {
0375     "clk26m",
0376     "msdcpll_ck",
0377     "msdcpll_d2",
0378     "univpll_d2_d4",
0379     "mainpll_d3_d2",
0380     "univpll_d2_d2"
0381 };
0382 
0383 static const char * const msdc30_1_parents[] = {
0384     "clk26m",
0385     "univpll_d3_d2",
0386     "mainpll_d3_d2",
0387     "mainpll_d7",
0388     "msdcpll_d2"
0389 };
0390 
0391 static const char * const audio_parents[] = {
0392     "clk26m",
0393     "mainpll_d5_d4",
0394     "mainpll_d7_d4",
0395     "mainpll_d2_d16"
0396 };
0397 
0398 static const char * const aud_intbus_parents[] = {
0399     "clk26m",
0400     "mainpll_d2_d4",
0401     "mainpll_d7_d2"
0402 };
0403 
0404 static const char * const fpwrap_ulposc_parents[] = {
0405     "osc_d10",
0406     "clk26m",
0407     "osc_d4",
0408     "osc_d8",
0409     "osc_d16"
0410 };
0411 
0412 static const char * const atb_parents[] = {
0413     "clk26m",
0414     "mainpll_d2_d2",
0415     "mainpll_d5"
0416 };
0417 
0418 static const char * const sspm_parents[] = {
0419     "clk26m",
0420     "univpll_d2_d4",
0421     "mainpll_d2_d2",
0422     "univpll_d2_d2",
0423     "mainpll_d3"
0424 };
0425 
0426 static const char * const dpi0_parents[] = {
0427     "clk26m",
0428     "tvdpll_d2",
0429     "tvdpll_d4",
0430     "tvdpll_d8",
0431     "tvdpll_d16"
0432 };
0433 
0434 static const char * const scam_parents[] = {
0435     "clk26m",
0436     "mainpll_d5_d2"
0437 };
0438 
0439 static const char * const disppwm_parents[] = {
0440     "clk26m",
0441     "univpll_d3_d4",
0442     "osc_d2",
0443     "osc_d4",
0444     "osc_d16"
0445 };
0446 
0447 static const char * const usb_top_parents[] = {
0448     "clk26m",
0449     "univpll_d5_d4",
0450     "univpll_d3_d4",
0451     "univpll_d5_d2"
0452 };
0453 
0454 static const char * const ssusb_top_xhci_parents[] = {
0455     "clk26m",
0456     "univpll_d5_d4",
0457     "univpll_d3_d4",
0458     "univpll_d5_d2"
0459 };
0460 
0461 static const char * const spm_parents[] = {
0462     "clk26m",
0463     "osc_d8",
0464     "mainpll_d2_d8"
0465 };
0466 
0467 static const char * const i2c_parents[] = {
0468     "clk26m",
0469     "mainpll_d2_d8",
0470     "univpll_d5_d2"
0471 };
0472 
0473 static const char * const seninf_parents[] = {
0474     "clk26m",
0475     "univpll_d7",
0476     "univpll_d3_d2",
0477     "univpll_d2_d2",
0478     "mainpll_d3",
0479     "mmpll_d4_d2",
0480     "mmpll_d7",
0481     "mmpll_d6"
0482 };
0483 
0484 static const char * const seninf1_parents[] = {
0485     "clk26m",
0486     "univpll_d7",
0487     "univpll_d3_d2",
0488     "univpll_d2_d2",
0489     "mainpll_d3",
0490     "mmpll_d4_d2",
0491     "mmpll_d7",
0492     "mmpll_d6"
0493 };
0494 
0495 static const char * const seninf2_parents[] = {
0496     "clk26m",
0497     "univpll_d7",
0498     "univpll_d3_d2",
0499     "univpll_d2_d2",
0500     "mainpll_d3",
0501     "mmpll_d4_d2",
0502     "mmpll_d7",
0503     "mmpll_d6"
0504 };
0505 
0506 static const char * const dxcc_parents[] = {
0507     "clk26m",
0508     "mainpll_d2_d2",
0509     "mainpll_d2_d4",
0510     "mainpll_d2_d8"
0511 };
0512 
0513 static const char * const aud_engen1_parents[] = {
0514     "clk26m",
0515     "apll1_d2",
0516     "apll1_d4",
0517     "apll1_d8"
0518 };
0519 
0520 static const char * const aud_engen2_parents[] = {
0521     "clk26m",
0522     "apll2_d2",
0523     "apll2_d4",
0524     "apll2_d8"
0525 };
0526 
0527 static const char * const faes_ufsfde_parents[] = {
0528     "clk26m",
0529     "mainpll_d2",
0530     "mainpll_d2_d2",
0531     "mainpll_d3",
0532     "mainpll_d2_d4",
0533     "univpll_d3"
0534 };
0535 
0536 static const char * const fufs_parents[] = {
0537     "clk26m",
0538     "mainpll_d2_d4",
0539     "mainpll_d2_d8",
0540     "mainpll_d2_d16"
0541 };
0542 
0543 static const char * const aud_1_parents[] = {
0544     "clk26m",
0545     "apll1_ck"
0546 };
0547 
0548 static const char * const aud_2_parents[] = {
0549     "clk26m",
0550     "apll2_ck"
0551 };
0552 
0553 static const char * const adsp_parents[] = {
0554     "clk26m",
0555     "mainpll_d3",
0556     "univpll_d2_d4",
0557     "univpll_d2",
0558     "mmpll_d4",
0559     "adsppll_d4",
0560     "adsppll_d6"
0561 };
0562 
0563 static const char * const dpmaif_parents[] = {
0564     "clk26m",
0565     "univpll_d2_d4",
0566     "mainpll_d3",
0567     "mainpll_d2_d2",
0568     "univpll_d2_d2",
0569     "univpll_d3"
0570 };
0571 
0572 static const char * const venc_parents[] = {
0573     "clk26m",
0574     "mmpll_d7",
0575     "mainpll_d3",
0576     "univpll_d2_d2",
0577     "mainpll_d2_d2",
0578     "univpll_d3",
0579     "mmpll_d6",
0580     "mainpll_d5",
0581     "mainpll_d3_d2",
0582     "mmpll_d4_d2",
0583     "univpll_d2_d4",
0584     "mmpll_d5",
0585     "univpll_192m_d2"
0586 
0587 };
0588 
0589 static const char * const vdec_parents[] = {
0590     "clk26m",
0591     "univpll_d2_d4",
0592     "mainpll_d3",
0593     "univpll_d2_d2",
0594     "mainpll_d2_d2",
0595     "univpll_d3",
0596     "univpll_d5",
0597     "univpll_d5_d2",
0598     "mainpll_d2",
0599     "univpll_d2",
0600     "univpll_192m_d2"
0601 };
0602 
0603 static const char * const camtm_parents[] = {
0604     "clk26m",
0605     "univpll_d7",
0606     "univpll_d3_d2",
0607     "univpll_d2_d2"
0608 };
0609 
0610 static const char * const pwm_parents[] = {
0611     "clk26m",
0612     "univpll_d2_d8"
0613 };
0614 
0615 static const char * const audio_h_parents[] = {
0616     "clk26m",
0617     "univpll_d7",
0618     "apll1_ck",
0619     "apll2_ck"
0620 };
0621 
0622 static const char * const camtg5_parents[] = {
0623     "clk26m",
0624     "univpll_192m_d8",
0625     "univpll_d3_d8",
0626     "univpll_192m_d4",
0627     "univpll_d3_d16",
0628     "csw_f26m_ck_d2",
0629     "univpll_192m_d16",
0630     "univpll_192m_d32"
0631 };
0632 
0633 /*
0634  * CRITICAL CLOCK:
0635  * axi_sel is the main bus clock of whole SOC.
0636  * spm_sel is the clock of the always-on co-processor.
0637  * sspm_sel is the clock of the always-on co-processor.
0638  */
0639 static const struct mtk_mux top_muxes[] = {
0640     /* CLK_CFG_0 */
0641     MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "axi_sel", axi_parents,
0642                    0x20, 0x24, 0x28, 0, 2, 7,
0643                    0x004, 0, CLK_IS_CRITICAL),
0644     MUX_GATE_CLR_SET_UPD(CLK_TOP_MM, "mm_sel", mm_parents,
0645                  0x20, 0x24, 0x28, 8, 3, 15, 0x004, 1),
0646     MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP, "scp_sel", scp_parents,
0647                  0x20, 0x24, 0x28, 16, 3, 23, 0x004, 2),
0648     /* CLK_CFG_1 */
0649     MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "img_sel", img_parents,
0650                  0x30, 0x34, 0x38, 0, 3, 7, 0x004, 4),
0651     MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "ipe_sel", ipe_parents,
0652                  0x30, 0x34, 0x38, 8, 3, 15, 0x004, 5),
0653     MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE, "dpe_sel", dpe_parents,
0654                  0x30, 0x34, 0x38, 16, 3, 23, 0x004, 6),
0655     MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "cam_sel", cam_parents,
0656                  0x30, 0x34, 0x38, 24, 4, 31, 0x004, 7),
0657     /* CLK_CFG_2 */
0658     MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "ccu_sel", ccu_parents,
0659                  0x40, 0x44, 0x48, 0, 4, 7, 0x004, 8),
0660     MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "dsp_sel", dsp_parents,
0661                  0x40, 0x44, 0x48, 8, 4, 15, 0x004, 9),
0662     MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "dsp1_sel", dsp1_parents,
0663                  0x40, 0x44, 0x48, 16, 4, 23, 0x004, 10),
0664     MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2, "dsp2_sel", dsp2_parents,
0665                  0x40, 0x44, 0x48, 24, 4, 31, 0x004, 11),
0666     /* CLK_CFG_3 */
0667     MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP3, "dsp3_sel", dsp3_parents,
0668                  0x50, 0x54, 0x58, 0, 4, 7, 0x004, 12),
0669     MUX_GATE_CLR_SET_UPD(CLK_TOP_IPU_IF, "ipu_if_sel", ipu_if_parents,
0670                  0x50, 0x54, 0x58, 8, 4, 15, 0x004, 13),
0671     MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG, "mfg_sel", mfg_parents,
0672                  0x50, 0x54, 0x58, 16, 2, 23, 0x004, 14),
0673     MUX_GATE_CLR_SET_UPD(CLK_TOP_F52M_MFG, "f52m_mfg_sel",
0674                  f52m_mfg_parents, 0x50, 0x54, 0x58,
0675                  24, 2, 31, 0x004, 15),
0676     /* CLK_CFG_4 */
0677     MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "camtg_sel", camtg_parents,
0678                  0x60, 0x64, 0x68, 0, 3, 7, 0x004, 16),
0679     MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "camtg2_sel", camtg2_parents,
0680                  0x60, 0x64, 0x68, 8, 3, 15, 0x004, 17),
0681     MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "camtg3_sel", camtg3_parents,
0682                  0x60, 0x64, 0x68, 16, 3, 23, 0x004, 18),
0683     MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4, "camtg4_sel", camtg4_parents,
0684                  0x60, 0x64, 0x68, 24, 3, 31, 0x004, 19),
0685     /* CLK_CFG_5 */
0686     MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "uart_sel", uart_parents,
0687                  0x70, 0x74, 0x78, 0, 1, 7, 0x004, 20),
0688     MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "spi_sel", spi_parents,
0689                  0x70, 0x74, 0x78, 8, 2, 15, 0x004, 21),
0690     MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "msdc50_hclk_sel",
0691                  msdc50_hclk_parents, 0x70, 0x74, 0x78,
0692                  16, 2, 23, 0x004, 22),
0693     MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "msdc50_0_sel",
0694                  msdc50_0_parents, 0x70, 0x74, 0x78,
0695                  24, 3, 31, 0x004, 23),
0696     /* CLK_CFG_6 */
0697     MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "msdc30_1_sel",
0698                  msdc30_1_parents, 0x80, 0x84, 0x88,
0699                  0, 3, 7, 0x004, 24),
0700     MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD, "audio_sel", audio_parents,
0701                  0x80, 0x84, 0x88, 8, 2, 15, 0x004, 25),
0702     MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "aud_intbus_sel",
0703                  aud_intbus_parents, 0x80, 0x84, 0x88,
0704                  16, 2, 23, 0x004, 26),
0705     MUX_GATE_CLR_SET_UPD(CLK_TOP_FPWRAP_ULPOSC, "fpwrap_ulposc_sel",
0706                  fpwrap_ulposc_parents, 0x80, 0x84, 0x88,
0707                  24, 3, 31, 0x004, 27),
0708     /* CLK_CFG_7 */
0709     MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB, "atb_sel", atb_parents,
0710                  0x90, 0x94, 0x98, 0, 2, 7, 0x004, 28),
0711     MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SSPM, "sspm_sel", sspm_parents,
0712                    0x90, 0x94, 0x98, 8, 3, 15,
0713                    0x004, 29, CLK_IS_CRITICAL),
0714     MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI0, "dpi0_sel", dpi0_parents,
0715                  0x90, 0x94, 0x98, 16, 3, 23, 0x004, 30),
0716     MUX_GATE_CLR_SET_UPD(CLK_TOP_SCAM, "scam_sel", scam_parents,
0717                  0x90, 0x94, 0x98, 24, 1, 31, 0x004, 0),
0718     /* CLK_CFG_8 */
0719     MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM, "disppwm_sel",
0720                  disppwm_parents, 0xa0, 0xa4, 0xa8,
0721                  0, 3, 7, 0x008, 1),
0722     MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "usb_top_sel",
0723                  usb_top_parents, 0xa0, 0xa4, 0xa8,
0724                  8, 2, 15, 0x008, 2),
0725     MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel",
0726                  ssusb_top_xhci_parents, 0xa0, 0xa4, 0xa8,
0727                  16, 2, 23, 0x008, 3),
0728     MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "spm_sel", spm_parents,
0729                    0xa0, 0xa4, 0xa8, 24, 2, 31,
0730                    0x008, 4, CLK_IS_CRITICAL),
0731     /* CLK_CFG_9 */
0732     MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "i2c_sel", i2c_parents,
0733                  0xb0, 0xb4, 0xb8, 0, 2, 7, 0x008, 5),
0734     MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF, "seninf_sel", seninf_parents,
0735                  0xb0, 0xb4, 0xb8, 8, 2, 15, 0x008, 6),
0736     MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "seninf1_sel",
0737                  seninf1_parents, 0xb0, 0xb4, 0xb8,
0738                  16, 2, 23, 0x008, 7),
0739     MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2, "seninf2_sel",
0740                  seninf2_parents, 0xb0, 0xb4, 0xb8,
0741                  24, 2, 31, 0x008, 8),
0742     /* CLK_CFG_10 */
0743     MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC, "dxcc_sel", dxcc_parents,
0744                  0xc0, 0xc4, 0xc8, 0, 2, 7, 0x008, 9),
0745     MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENG1, "aud_eng1_sel",
0746                  aud_engen1_parents, 0xc0, 0xc4, 0xc8,
0747                  8, 2, 15, 0x008, 10),
0748     MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENG2, "aud_eng2_sel",
0749                  aud_engen2_parents, 0xc0, 0xc4, 0xc8,
0750                  16, 2, 23, 0x008, 11),
0751     MUX_GATE_CLR_SET_UPD(CLK_TOP_FAES_UFSFDE, "faes_ufsfde_sel",
0752                  faes_ufsfde_parents, 0xc0, 0xc4, 0xc8,
0753                  24, 3, 31,
0754                  0x008, 12),
0755     /* CLK_CFG_11 */
0756     MUX_GATE_CLR_SET_UPD(CLK_TOP_FUFS, "fufs_sel", fufs_parents,
0757                  0xd0, 0xd4, 0xd8, 0, 2, 7, 0x008, 13),
0758     MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1, "aud_1_sel", aud_1_parents,
0759                  0xd0, 0xd4, 0xd8, 8, 1, 15, 0x008, 14),
0760     MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2, "aud_2_sel", aud_2_parents,
0761                  0xd0, 0xd4, 0xd8, 16, 1, 23, 0x008, 15),
0762     MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP, "adsp_sel", adsp_parents,
0763                  0xd0, 0xd4, 0xd8, 24, 3, 31, 0x008, 16),
0764     /* CLK_CFG_12 */
0765     MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF, "dpmaif_sel", dpmaif_parents,
0766                  0xe0, 0xe4, 0xe8, 0, 3, 7, 0x008, 17),
0767     MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC, "venc_sel", venc_parents,
0768                  0xe0, 0xe4, 0xe8, 8, 4, 15, 0x008, 18),
0769     MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC, "vdec_sel", vdec_parents,
0770                  0xe0, 0xe4, 0xe8, 16, 4, 23, 0x008, 19),
0771     MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "camtm_sel", camtm_parents,
0772                  0xe0, 0xe4, 0xe8, 24, 2, 31, 0x004, 20),
0773     /* CLK_CFG_13 */
0774     MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "pwm_sel", pwm_parents,
0775                  0xf0, 0xf4, 0xf8, 0, 1, 7, 0x008, 21),
0776     MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_H, "audio_h_sel",
0777                  audio_h_parents, 0xf0, 0xf4, 0xf8,
0778                  8, 2, 15, 0x008, 22),
0779     MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5, "camtg5_sel", camtg5_parents,
0780                  0xf0, 0xf4, 0xf8, 24, 3, 31, 0x008, 24),
0781 };
0782 
0783 static const char * const i2s0_m_ck_parents[] = {
0784     "aud_1_sel",
0785     "aud_2_sel"
0786 };
0787 
0788 static const char * const i2s1_m_ck_parents[] = {
0789     "aud_1_sel",
0790     "aud_2_sel"
0791 };
0792 
0793 static const char * const i2s2_m_ck_parents[] = {
0794     "aud_1_sel",
0795     "aud_2_sel"
0796 };
0797 
0798 static const char * const i2s3_m_ck_parents[] = {
0799     "aud_1_sel",
0800     "aud_2_sel"
0801 };
0802 
0803 static const char * const i2s4_m_ck_parents[] = {
0804     "aud_1_sel",
0805     "aud_2_sel"
0806 };
0807 
0808 static const char * const i2s5_m_ck_parents[] = {
0809     "aud_1_sel",
0810     "aud_2_sel"
0811 };
0812 
0813 static const struct mtk_composite top_aud_muxes[] = {
0814     MUX(CLK_TOP_I2S0_M_SEL, "i2s0_m_ck_sel", i2s0_m_ck_parents,
0815         0x320, 8, 1),
0816     MUX(CLK_TOP_I2S1_M_SEL, "i2s1_m_ck_sel", i2s1_m_ck_parents,
0817         0x320, 9, 1),
0818     MUX(CLK_TOP_I2S2_M_SEL, "i2s2_m_ck_sel", i2s2_m_ck_parents,
0819         0x320, 10, 1),
0820     MUX(CLK_TOP_I2S3_M_SEL, "i2s3_m_ck_sel", i2s3_m_ck_parents,
0821         0x320, 11, 1),
0822     MUX(CLK_TOP_I2S4_M_SEL, "i2s4_m_ck_sel", i2s4_m_ck_parents,
0823         0x320, 12, 1),
0824     MUX(CLK_TOP_I2S5_M_SEL, "i2s5_m_ck_sel", i2s5_m_ck_parents,
0825         0x328, 20, 1),
0826 };
0827 
0828 static struct mtk_composite top_aud_divs[] = {
0829     DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "i2s0_m_ck_sel",
0830          0x320, 2, 0x324, 8, 0),
0831     DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "i2s1_m_ck_sel",
0832          0x320, 3, 0x324, 8, 8),
0833     DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "i2s2_m_ck_sel",
0834          0x320, 4, 0x324, 8, 16),
0835     DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "i2s3_m_ck_sel",
0836          0x320, 5, 0x324, 8, 24),
0837     DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "i2s4_m_ck_sel",
0838          0x320, 6, 0x328, 8, 0),
0839     DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4",
0840          0x320, 7, 0x328, 8, 8),
0841     DIV_GATE(CLK_TOP_APLL12_DIV5, "apll12_div5", "i2s5_m_ck_sel",
0842          0x328, 16, 0x328, 4, 28),
0843 };
0844 
0845 static const struct mtk_gate_regs infra0_cg_regs = {
0846     .set_ofs = 0x80,
0847     .clr_ofs = 0x84,
0848     .sta_ofs = 0x90,
0849 };
0850 
0851 static const struct mtk_gate_regs infra1_cg_regs = {
0852     .set_ofs = 0x88,
0853     .clr_ofs = 0x8c,
0854     .sta_ofs = 0x94,
0855 };
0856 
0857 static const struct mtk_gate_regs infra2_cg_regs = {
0858     .set_ofs = 0xa4,
0859     .clr_ofs = 0xa8,
0860     .sta_ofs = 0xac,
0861 };
0862 
0863 static const struct mtk_gate_regs infra3_cg_regs = {
0864     .set_ofs = 0xc0,
0865     .clr_ofs = 0xc4,
0866     .sta_ofs = 0xc8,
0867 };
0868 
0869 #define GATE_INFRA0(_id, _name, _parent, _shift)        \
0870     GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift,  \
0871         &mtk_clk_gate_ops_setclr)
0872 #define GATE_INFRA1(_id, _name, _parent, _shift)        \
0873     GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift,  \
0874         &mtk_clk_gate_ops_setclr)
0875 #define GATE_INFRA2(_id, _name, _parent, _shift)        \
0876     GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift,  \
0877         &mtk_clk_gate_ops_setclr)
0878 #define GATE_INFRA3(_id, _name, _parent, _shift)        \
0879     GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift,  \
0880         &mtk_clk_gate_ops_setclr)
0881 
0882 static const struct mtk_gate infra_clks[] = {
0883     /* INFRA0 */
0884     GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr",
0885             "axi_sel", 0),
0886     GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap",
0887             "axi_sel", 1),
0888     GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md",
0889             "axi_sel", 2),
0890     GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn",
0891             "axi_sel", 3),
0892     GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp",
0893             "axi_sel", 4),
0894     GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej",
0895             "f_f26m_ck", 5),
0896     GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt",
0897             "axi_sel", 6),
0898     GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb",
0899             "axi_sel", 8),
0900     GATE_INFRA0(CLK_INFRA_GCE, "infra_gce",
0901             "axi_sel", 9),
0902     GATE_INFRA0(CLK_INFRA_THERM, "infra_therm",
0903             "axi_sel", 10),
0904     GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0",
0905             "i2c_sel", 11),
0906     GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1",
0907             "i2c_sel", 12),
0908     GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2",
0909             "i2c_sel", 13),
0910     GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3",
0911             "i2c_sel", 14),
0912     GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk",
0913             "pwm_sel", 15),
0914     GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1",
0915             "pwm_sel", 16),
0916     GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2",
0917             "pwm_sel", 17),
0918     GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3",
0919             "pwm_sel", 18),
0920     GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4",
0921             "pwm_sel", 19),
0922     GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
0923             "pwm_sel", 21),
0924     GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
0925             "uart_sel", 22),
0926     GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
0927             "uart_sel", 23),
0928     GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
0929             "uart_sel", 24),
0930     GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3",
0931             "uart_sel", 25),
0932     GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m",
0933             "axi_sel", 27),
0934     GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc",
0935             "axi_sel", 28),
0936     GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif",
0937             "axi_sel", 31),
0938     /* INFRA1 */
0939     GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0",
0940             "spi_sel", 1),
0941     GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0",
0942             "msdc50_hclk_sel", 2),
0943     GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1",
0944             "axi_sel", 4),
0945     GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2",
0946             "axi_sel", 5),
0947     GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck",
0948             "msdc50_0_sel", 6),
0949     GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc",
0950             "f_f26m_ck", 7),
0951     GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu",
0952             "axi_sel", 8),
0953     GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng",
0954             "axi_sel", 9),
0955     GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc",
0956             "f_f26m_ck", 10),
0957     GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum",
0958             "axi_sel", 11),
0959     GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap",
0960             "axi_sel", 12),
0961     GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md",
0962             "axi_sel", 13),
0963     GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md",
0964             "f_f26m_ck", 14),
0965     GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck",
0966             "msdc30_1_sel", 16),
0967     GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck",
0968             "msdc30_2_sel", 17),
0969     GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma",
0970             "axi_sel", 18),
0971     GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu",
0972             "axi_sel", 19),
0973     GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc",
0974             "axi_sel", 20),
0975     GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap",
0976             "axi_sel", 23),
0977     GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys",
0978             "axi_sel", 24),
0979     GATE_INFRA1(CLK_INFRA_AUD, "infra_audio",
0980             "axi_sel", 25),
0981     GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md",
0982             "axi_sel", 26),
0983     GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core",
0984             "dxcc_sel", 27),
0985     GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao",
0986             "dxcc_sel", 28),
0987     GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk",
0988             "axi_sel", 30),
0989     GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
0990             "f_f26m_ck", 31),
0991     /* INFRA2 */
0992     GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx",
0993             "f_f26m_ck", 0),
0994     GATE_INFRA2(CLK_INFRA_USB, "infra_usb",
0995             "usb_top_sel", 1),
0996     GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm",
0997             "axi_sel", 2),
0998     GATE_INFRA2(CLK_INFRA_AUD_26M_BCLK,
0999             "infracfg_ao_audio_26m_bclk", "f_f26m_ck", 4),
1000     GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1",
1001             "spi_sel", 6),
1002     GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4",
1003             "i2c_sel", 7),
1004     GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share",
1005             "f_f26m_ck", 8),
1006     GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2",
1007             "spi_sel", 9),
1008     GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3",
1009             "spi_sel", 10),
1010     GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck",
1011             "fufs_sel", 11),
1012     GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick",
1013             "fufs_sel", 12),
1014     GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck",
1015             "fufs_sel", 13),
1016     GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk",
1017             "axi_sel", 14),
1018     GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist",
1019             "axi_sel", 16),
1020     GATE_INFRA2(CLK_INFRA_SSPM_BUS_HCLK, "infra_sspm_bus_hclk",
1021             "axi_sel", 17),
1022     GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5",
1023             "i2c_sel", 18),
1024     GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter",
1025             "i2c_sel", 19),
1026     GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm",
1027             "i2c_sel", 20),
1028     GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter",
1029             "i2c_sel", 21),
1030     GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm",
1031             "i2c_sel", 22),
1032     GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter",
1033             "i2c_sel", 23),
1034     GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm",
1035             "i2c_sel", 24),
1036     GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4",
1037             "spi_sel", 25),
1038     GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5",
1039             "spi_sel", 26),
1040     GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma",
1041             "axi_sel", 27),
1042     GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs",
1043             "fufs_sel", 28),
1044     GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde",
1045             "faes_ufsfde_sel", 29),
1046     GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick",
1047             "fufs_sel", 30),
1048     GATE_INFRA2(CLK_INFRA_SSUSB_XHCI, "infra_ssusb_xhci",
1049             "ssusb_top_xhci_sel", 31),
1050     /* INFRA3 */
1051     GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self",
1052             "msdc50_0_sel", 0),
1053     GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self",
1054             "msdc50_0_sel", 1),
1055     GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self",
1056             "msdc50_0_sel", 2),
1057     GATE_INFRA3(CLK_INFRA_SSPM_26M_SELF, "infra_sspm_26m_self",
1058             "f_f26m_ck", 3),
1059     GATE_INFRA3(CLK_INFRA_SSPM_32K_SELF, "infra_sspm_32k_self",
1060             "f_f26m_ck", 4),
1061     GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi",
1062             "axi_sel", 5),
1063     GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6",
1064             "i2c_sel", 6),
1065     GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0",
1066             "msdc50_hclk_sel", 7),
1067     GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0",
1068             "msdc50_hclk_sel", 8),
1069     GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap",
1070             "axi_sel", 16),
1071     GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md",
1072             "axi_sel", 17),
1073     GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap",
1074             "axi_sel", 18),
1075     GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md",
1076             "axi_sel", 19),
1077     GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m",
1078             "f_f26m_ck", 20),
1079     GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk",
1080             "axi_sel", 21),
1081     GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7",
1082             "i2c_sel", 22),
1083     GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8",
1084             "i2c_sel", 23),
1085     GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc",
1086             "msdc50_0_sel", 24),
1087     GATE_INFRA3(CLK_INFRA_DPMAIF_CK, "infra_dpmaif",
1088             "dpmaif_sel", 26),
1089     GATE_INFRA3(CLK_INFRA_FADSP, "infra_fadsp",
1090             "adsp_sel", 27),
1091     GATE_INFRA3(CLK_INFRA_CCIF4_AP, "infra_ccif4_ap",
1092             "axi_sel", 28),
1093     GATE_INFRA3(CLK_INFRA_CCIF4_MD, "infra_ccif4_md",
1094             "axi_sel", 29),
1095     GATE_INFRA3(CLK_INFRA_SPI6, "infra_spi6",
1096             "spi_sel", 30),
1097     GATE_INFRA3(CLK_INFRA_SPI7, "infra_spi7",
1098             "spi_sel", 31),
1099 };
1100 
1101 static const struct mtk_gate_regs apmixed_cg_regs = {
1102     .set_ofs = 0x20,
1103     .clr_ofs = 0x20,
1104     .sta_ofs = 0x20,
1105 };
1106 
1107 #define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \
1108     GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs,       \
1109         _shift, &mtk_clk_gate_ops_no_setclr_inv, _flags)
1110 
1111 #define GATE_APMIXED(_id, _name, _parent, _shift)   \
1112     GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0)
1113 
1114 /*
1115  * CRITICAL CLOCK:
1116  * apmixed_appll26m is the toppest clock gate of all PLLs.
1117  */
1118 static const struct mtk_gate apmixed_clks[] = {
1119     GATE_APMIXED(CLK_APMIXED_SSUSB26M, "apmixed_ssusb26m",
1120              "f_f26m_ck", 4),
1121     GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL26M, "apmixed_appll26m",
1122                "f_f26m_ck", 5, CLK_IS_CRITICAL),
1123     GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m",
1124              "f_f26m_ck", 6),
1125     GATE_APMIXED(CLK_APMIXED_MDPLLGP26M, "apmixed_mdpll26m",
1126              "f_f26m_ck", 7),
1127     GATE_APMIXED(CLK_APMIXED_MM_F26M, "apmixed_mmsys26m",
1128              "f_f26m_ck", 8),
1129     GATE_APMIXED(CLK_APMIXED_UFS26M, "apmixed_ufs26m",
1130              "f_f26m_ck", 9),
1131     GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m",
1132              "f_f26m_ck", 11),
1133     GATE_APMIXED(CLK_APMIXED_MEMPLL26M, "apmixed_mempll26m",
1134              "f_f26m_ck", 13),
1135     GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m",
1136              "f_f26m_ck", 14),
1137     GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m",
1138              "f_f26m_ck", 16),
1139     GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m",
1140              "f_f26m_ck", 17),
1141 };
1142 
1143 #define MT6779_PLL_FMAX     (3800UL * MHZ)
1144 #define MT6779_PLL_FMIN     (1500UL * MHZ)
1145 
1146 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags,     \
1147             _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg,    \
1148             _pd_shift, _tuner_reg,  _tuner_en_reg,      \
1149             _tuner_en_bit, _pcw_reg, _pcw_shift,        \
1150             _pcw_chg_reg, _div_table) {         \
1151         .id = _id,                      \
1152         .name = _name,                      \
1153         .reg = _reg,                        \
1154         .pwr_reg = _pwr_reg,                    \
1155         .en_mask = _en_mask,                    \
1156         .flags = _flags,                    \
1157         .rst_bar_mask = _rst_bar_mask,              \
1158         .fmax = MT6779_PLL_FMAX,                \
1159         .fmin = MT6779_PLL_FMIN,                \
1160         .pcwbits = _pcwbits,                    \
1161         .pcwibits = _pcwibits,                  \
1162         .pd_reg = _pd_reg,                  \
1163         .pd_shift = _pd_shift,                  \
1164         .tuner_reg = _tuner_reg,                \
1165         .tuner_en_reg = _tuner_en_reg,              \
1166         .tuner_en_bit = _tuner_en_bit,              \
1167         .pcw_reg = _pcw_reg,                    \
1168         .pcw_shift = _pcw_shift,                \
1169         .pcw_chg_reg = _pcw_chg_reg,                \
1170         .div_table = _div_table,                \
1171     }
1172 
1173 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags,       \
1174             _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg,    \
1175             _pd_shift, _tuner_reg, _tuner_en_reg,       \
1176             _tuner_en_bit, _pcw_reg, _pcw_shift,        \
1177             _pcw_chg_reg)                   \
1178         PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1179             _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg,    \
1180             _pd_shift, _tuner_reg, _tuner_en_reg,       \
1181             _tuner_en_bit, _pcw_reg, _pcw_shift,        \
1182             _pcw_chg_reg, NULL)
1183 
1184 static const struct mtk_pll_data plls[] = {
1185     PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0,
1186         PLL_AO, 0, 22, 8, 0x0204, 24, 0, 0, 0, 0x0204, 0, 0),
1187     PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0210, 0x021C, 0,
1188         PLL_AO, 0, 22, 8, 0x0214, 24, 0, 0, 0, 0x0214, 0, 0),
1189     PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x02A0, 0x02AC, 0,
1190         PLL_AO, 0, 22, 8, 0x02A4, 24, 0, 0, 0, 0x02A4, 0, 0),
1191     PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0,
1192         (HAVE_RST_BAR), BIT(24), 22, 8, 0x0234, 24, 0, 0, 0,
1193         0x0234, 0, 0),
1194     PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0240, 0x024C, 0,
1195         (HAVE_RST_BAR), BIT(24), 22, 8, 0x0244, 24,
1196         0, 0, 0, 0x0244, 0, 0),
1197     PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0250, 0x025C, 0,
1198         0, 0, 22, 8, 0x0254, 24, 0, 0, 0, 0x0254, 0, 0),
1199     PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0260, 0x026C, 0,
1200         0, 0, 22, 8, 0x0264, 24, 0, 0, 0, 0x0264, 0, 0),
1201     PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0,
1202         0, 0, 22, 8, 0x0274, 24, 0, 0, 0, 0x0274, 0, 0),
1203     PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x02b0, 0x02bC, 0,
1204         (HAVE_RST_BAR), BIT(23), 22, 8, 0x02b4, 24,
1205         0, 0, 0, 0x02b4, 0, 0),
1206     PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0280, 0x028C, 0,
1207         (HAVE_RST_BAR), BIT(23), 22, 8, 0x0284, 24,
1208         0, 0, 0, 0x0284, 0, 0),
1209     PLL(CLK_APMIXED_APLL1, "apll1", 0x02C0, 0x02D0, 0,
1210         0, 0, 32, 8, 0x02C0, 1, 0, 0x14, 0, 0x02C4, 0, 0x2C0),
1211     PLL(CLK_APMIXED_APLL2, "apll2", 0x02D4, 0x02E4, 0,
1212         0, 0, 32, 8, 0x02D4, 1, 0, 0x14, 1, 0x02D8, 0, 0x02D4),
1213 };
1214 
1215 static int clk_mt6779_apmixed_probe(struct platform_device *pdev)
1216 {
1217     struct clk_hw_onecell_data *clk_data;
1218     struct device_node *node = pdev->dev.of_node;
1219 
1220     clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
1221 
1222     mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
1223 
1224     mtk_clk_register_gates(node, apmixed_clks,
1225                    ARRAY_SIZE(apmixed_clks), clk_data);
1226 
1227     return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1228 }
1229 
1230 static int clk_mt6779_top_probe(struct platform_device *pdev)
1231 {
1232     void __iomem *base;
1233     struct clk_hw_onecell_data *clk_data;
1234     struct device_node *node = pdev->dev.of_node;
1235 
1236     base = devm_platform_ioremap_resource(pdev, 0);
1237     if (IS_ERR(base))
1238         return PTR_ERR(base);
1239 
1240     clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1241 
1242     mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
1243                     clk_data);
1244 
1245     mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
1246 
1247     mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes),
1248                    node, &mt6779_clk_lock, clk_data);
1249 
1250     mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes),
1251                     base, &mt6779_clk_lock, clk_data);
1252 
1253     mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs),
1254                     base, &mt6779_clk_lock, clk_data);
1255 
1256     return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1257 }
1258 
1259 static int clk_mt6779_infra_probe(struct platform_device *pdev)
1260 {
1261     struct clk_hw_onecell_data *clk_data;
1262     struct device_node *node = pdev->dev.of_node;
1263 
1264     clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
1265 
1266     mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
1267                    clk_data);
1268 
1269     return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1270 }
1271 
1272 static const struct of_device_id of_match_clk_mt6779[] = {
1273     {
1274         .compatible = "mediatek,mt6779-apmixed",
1275         .data = clk_mt6779_apmixed_probe,
1276     }, {
1277         .compatible = "mediatek,mt6779-topckgen",
1278         .data = clk_mt6779_top_probe,
1279     }, {
1280         .compatible = "mediatek,mt6779-infracfg_ao",
1281         .data = clk_mt6779_infra_probe,
1282     }, {
1283         /* sentinel */
1284     }
1285 };
1286 
1287 static int clk_mt6779_probe(struct platform_device *pdev)
1288 {
1289     int (*clk_probe)(struct platform_device *pdev);
1290     int r;
1291 
1292     clk_probe = of_device_get_match_data(&pdev->dev);
1293     if (!clk_probe)
1294         return -EINVAL;
1295 
1296     r = clk_probe(pdev);
1297     if (r)
1298         dev_err(&pdev->dev,
1299             "could not register clock provider: %s: %d\n",
1300             pdev->name, r);
1301 
1302     return r;
1303 }
1304 
1305 static struct platform_driver clk_mt6779_drv = {
1306     .probe = clk_mt6779_probe,
1307     .driver = {
1308         .name = "clk-mt6779",
1309         .of_match_table = of_match_clk_mt6779,
1310     },
1311 };
1312 
1313 static int __init clk_mt6779_init(void)
1314 {
1315     return platform_driver_register(&clk_mt6779_drv);
1316 }
1317 
1318 arch_initcall(clk_mt6779_init);
1319 MODULE_LICENSE("GPL");
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