clk/mediatek/clk-mt6779-mm.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2019 MediaTek Inc.
0004  * Author: Wendell Lin <wendell.lin@mediatek.com>
0005  */
0006
0007 #include <linux/module.h>
0008 #include <linux/clk-provider.h>
0009 #include <linux/platform_device.h>
0010 #include <dt-bindings/clock/mt6779-clk.h>
0011
0012 #include "clk-mtk.h"
0013 #include "clk-gate.h"
0014
0015 static const struct mtk_gate_regs mm0_cg_regs = {
0016     .set_ofs = 0x0104,
0017     .clr_ofs = 0x0108,
0018     .sta_ofs = 0x0100,
0019 };
0020
0021 static const struct mtk_gate_regs mm1_cg_regs = {
0022     .set_ofs = 0x0114,
0023     .clr_ofs = 0x0118,
0024     .sta_ofs = 0x0110,
0025 };
0026
0027 #define GATE_MM0(_id, _name, _parent, _shift)           \
0028     GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, \
0029         &mtk_clk_gate_ops_setclr)
0030 #define GATE_MM1(_id, _name, _parent, _shift)           \
0031     GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, \
0032         &mtk_clk_gate_ops_setclr)
0033
0034 static const struct mtk_gate mm_clks[] = {
0035     /* MM0 */
0036     GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
0037     GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
0038     GATE_MM0(CLK_MM_SMI_LARB1, "mm_smi_larb1", "mm_sel", 2),
0039     GATE_MM0(CLK_MM_GALS_COMM0, "mm_gals_comm0", "mm_sel", 3),
0040     GATE_MM0(CLK_MM_GALS_COMM1, "mm_gals_comm1", "mm_sel", 4),
0041     GATE_MM0(CLK_MM_GALS_CCU2MM, "mm_gals_ccu2mm", "mm_sel", 5),
0042     GATE_MM0(CLK_MM_GALS_IPU12MM, "mm_gals_ipu12mm", "mm_sel", 6),
0043     GATE_MM0(CLK_MM_GALS_IMG2MM, "mm_gals_img2mm", "mm_sel", 7),
0044     GATE_MM0(CLK_MM_GALS_CAM2MM, "mm_gals_cam2mm", "mm_sel", 8),
0045     GATE_MM0(CLK_MM_GALS_IPU2MM, "mm_gals_ipu2mm", "mm_sel", 9),
0046     GATE_MM0(CLK_MM_MDP_DL_TXCK, "mm_mdp_dl_txck", "mm_sel", 10),
0047     GATE_MM0(CLK_MM_IPU_DL_TXCK, "mm_ipu_dl_txck", "mm_sel", 11),
0048     GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 12),
0049     GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 13),
0050     GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 14),
0051     GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 15),
0052     GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 16),
0053     GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 17),
0054     GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 18),
0055     GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 19),
0056     GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 20),
0057     GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 21),
0058     GATE_MM0(CLK_MM_DISP_OVL1_2L, "mm_disp_ovl1_2l", "mm_sel", 22),
0059     GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 23),
0060     GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 24),
0061     GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 25),
0062     GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 26),
0063     GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "mm_sel", 27),
0064     GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "mm_sel", 28),
0065     GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "mm_sel", 29),
0066     GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "mm_sel", 30),
0067     GATE_MM0(CLK_MM_DISP_SPLIT, "mm_disp_split", "mm_sel", 31),
0068     /* MM1 */
0069     GATE_MM1(CLK_MM_DSI0_MM_CK, "mm_dsi0_mmck", "mm_sel", 0),
0070     GATE_MM1(CLK_MM_DSI0_IF_CK, "mm_dsi0_ifck", "mm_sel", 1),
0071     GATE_MM1(CLK_MM_DPI_MM_CK, "mm_dpi_mmck", "mm_sel", 2),
0072     GATE_MM1(CLK_MM_DPI_IF_CK, "mm_dpi_ifck", "dpi0_sel", 3),
0073     GATE_MM1(CLK_MM_FAKE_ENG2, "mm_fake_eng2", "mm_sel", 4),
0074     GATE_MM1(CLK_MM_MDP_DL_RX_CK, "mm_mdp_dl_rxck", "mm_sel", 5),
0075     GATE_MM1(CLK_MM_IPU_DL_RX_CK, "mm_ipu_dl_rxck", "mm_sel", 6),
0076     GATE_MM1(CLK_MM_26M, "mm_26m", "f_f26m_ck", 7),
0077     GATE_MM1(CLK_MM_MM_R2Y, "mm_mmsys_r2y", "mm_sel", 8),
0078     GATE_MM1(CLK_MM_DISP_RSZ, "mm_disp_rsz", "mm_sel", 9),
0079     GATE_MM1(CLK_MM_MDP_AAL, "mm_mdp_aal", "mm_sel", 10),
0080     GATE_MM1(CLK_MM_MDP_HDR, "mm_mdp_hdr", "mm_sel", 11),
0081     GATE_MM1(CLK_MM_DBI_MM_CK, "mm_dbi_mmck", "mm_sel", 12),
0082     GATE_MM1(CLK_MM_DBI_IF_CK, "mm_dbi_ifck", "dpi0_sel", 13),
0083     GATE_MM1(CLK_MM_DISP_POSTMASK0, "mm_disp_pm0", "mm_sel", 14),
0084     GATE_MM1(CLK_MM_DISP_HRT_BW, "mm_disp_hrt_bw", "mm_sel", 15),
0085     GATE_MM1(CLK_MM_DISP_OVL_FBDC, "mm_disp_ovl_fbdc", "mm_sel", 16),
0086 };
0087
0088 static int clk_mt6779_mm_probe(struct platform_device *pdev)
0089 {
0090     struct device *dev = &pdev->dev;
0091     struct device_node *node = dev->parent->of_node;
0092     struct clk_hw_onecell_data *clk_data;
0093
0094     clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
0095
0096     mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
0097                    clk_data);
0098
0099     return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0100 }
0101
0102 static struct platform_driver clk_mt6779_mm_drv = {
0103     .probe = clk_mt6779_mm_probe,
0104     .driver = {
0105         .name = "clk-mt6779-mm",
0106     },
0107 };
0108
0109 module_platform_driver(clk_mt6779_mm_drv);
0110 MODULE_LICENSE("GPL");