clk/mediatek/clk-mt6779-mfg.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2019 MediaTek Inc.
0004  * Author: Wendell Lin <wendell.lin@mediatek.com>
0005  */
0006
0007 #include <linux/module.h>
0008 #include <linux/clk-provider.h>
0009 #include <linux/platform_device.h>
0010
0011 #include "clk-mtk.h"
0012 #include "clk-gate.h"
0013
0014 #include <dt-bindings/clock/mt6779-clk.h>
0015
0016 static const struct mtk_gate_regs mfg_cg_regs = {
0017     .set_ofs = 0x4,
0018     .clr_ofs = 0x8,
0019     .sta_ofs = 0x0,
0020 };
0021
0022 #define GATE_MFG(_id, _name, _parent, _shift)           \
0023     GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, \
0024         &mtk_clk_gate_ops_setclr)
0025
0026 static const struct mtk_gate mfg_clks[] = {
0027     GATE_MFG(CLK_MFGCFG_BG3D, "mfg_bg3d", "mfg_sel", 0),
0028 };
0029
0030 static int clk_mt6779_mfg_probe(struct platform_device *pdev)
0031 {
0032     struct clk_hw_onecell_data *clk_data;
0033     struct device_node *node = pdev->dev.of_node;
0034
0035     clk_data = mtk_alloc_clk_data(CLK_MFGCFG_NR_CLK);
0036
0037     mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks),
0038                    clk_data);
0039
0040     return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0041 }
0042
0043 static const struct of_device_id of_match_clk_mt6779_mfg[] = {
0044     { .compatible = "mediatek,mt6779-mfgcfg", },
0045     {}
0046 };
0047
0048 static struct platform_driver clk_mt6779_mfg_drv = {
0049     .probe = clk_mt6779_mfg_probe,
0050     .driver = {
0051         .name = "clk-mt6779-mfg",
0052         .of_match_table = of_match_clk_mt6779_mfg,
0053     },
0054 };
0055
0056 module_platform_driver(clk_mt6779_mfg_drv);
0057 MODULE_LICENSE("GPL");