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0007 #include <linux/clk-provider.h>
0008 #include <linux/platform_device.h>
0009
0010 #include "clk-mtk.h"
0011 #include "clk-gate.h"
0012
0013 #include <dt-bindings/clock/mt6765-clk.h>
0014
0015 static const struct mtk_gate_regs venc_cg_regs = {
0016 .set_ofs = 0x4,
0017 .clr_ofs = 0x8,
0018 .sta_ofs = 0x0,
0019 };
0020
0021 #define GATE_VENC(_id, _name, _parent, _shift) { \
0022 .id = _id, \
0023 .name = _name, \
0024 .parent_name = _parent, \
0025 .regs = &venc_cg_regs, \
0026 .shift = _shift, \
0027 .ops = &mtk_clk_gate_ops_setclr_inv, \
0028 }
0029
0030 static const struct mtk_gate venc_clks[] = {
0031 GATE_VENC(CLK_VENC_SET0_LARB, "venc_set0_larb", "mm_ck", 0),
0032 GATE_VENC(CLK_VENC_SET1_VENC, "venc_set1_venc", "mm_ck", 4),
0033 GATE_VENC(CLK_VENC_SET2_JPGENC, "jpgenc", "mm_ck", 8),
0034 GATE_VENC(CLK_VENC_SET3_VDEC, "venc_set3_vdec", "mm_ck", 12),
0035 };
0036
0037 static int clk_mt6765_vcodec_probe(struct platform_device *pdev)
0038 {
0039 struct clk_hw_onecell_data *clk_data;
0040 int r;
0041 struct device_node *node = pdev->dev.of_node;
0042
0043 clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK);
0044
0045 mtk_clk_register_gates(node, venc_clks,
0046 ARRAY_SIZE(venc_clks), clk_data);
0047
0048 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0049
0050 if (r)
0051 pr_err("%s(): could not register clock provider: %d\n",
0052 __func__, r);
0053
0054 return r;
0055 }
0056
0057 static const struct of_device_id of_match_clk_mt6765_vcodec[] = {
0058 { .compatible = "mediatek,mt6765-vcodecsys", },
0059 {}
0060 };
0061
0062 static struct platform_driver clk_mt6765_vcodec_drv = {
0063 .probe = clk_mt6765_vcodec_probe,
0064 .driver = {
0065 .name = "clk-mt6765-vcodec",
0066 .of_match_table = of_match_clk_mt6765_vcodec,
0067 },
0068 };
0069
0070 builtin_platform_driver(clk_mt6765_vcodec_drv);