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0007 #include <linux/clk-provider.h>
0008 #include <linux/platform_device.h>
0009
0010 #include "clk-mtk.h"
0011 #include "clk-gate.h"
0012
0013 #include <dt-bindings/clock/mt6765-clk.h>
0014
0015 static const struct mtk_gate_regs mipi0a_cg_regs = {
0016 .set_ofs = 0x80,
0017 .clr_ofs = 0x80,
0018 .sta_ofs = 0x80,
0019 };
0020
0021 #define GATE_MIPI0A(_id, _name, _parent, _shift) { \
0022 .id = _id, \
0023 .name = _name, \
0024 .parent_name = _parent, \
0025 .regs = &mipi0a_cg_regs, \
0026 .shift = _shift, \
0027 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
0028 }
0029
0030 static const struct mtk_gate mipi0a_clks[] = {
0031 GATE_MIPI0A(CLK_MIPI0A_CSR_CSI_EN_0A,
0032 "mipi0a_csr_0a", "f_fseninf_ck", 1),
0033 };
0034
0035 static int clk_mt6765_mipi0a_probe(struct platform_device *pdev)
0036 {
0037 struct clk_hw_onecell_data *clk_data;
0038 int r;
0039 struct device_node *node = pdev->dev.of_node;
0040
0041 clk_data = mtk_alloc_clk_data(CLK_MIPI0A_NR_CLK);
0042
0043 mtk_clk_register_gates(node, mipi0a_clks,
0044 ARRAY_SIZE(mipi0a_clks), clk_data);
0045
0046 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0047
0048 if (r)
0049 pr_err("%s(): could not register clock provider: %d\n",
0050 __func__, r);
0051
0052 return r;
0053 }
0054
0055 static const struct of_device_id of_match_clk_mt6765_mipi0a[] = {
0056 { .compatible = "mediatek,mt6765-mipi0a", },
0057 {}
0058 };
0059
0060 static struct platform_driver clk_mt6765_mipi0a_drv = {
0061 .probe = clk_mt6765_mipi0a_probe,
0062 .driver = {
0063 .name = "clk-mt6765-mipi0a",
0064 .of_match_table = of_match_clk_mt6765_mipi0a,
0065 },
0066 };
0067
0068 builtin_platform_driver(clk_mt6765_mipi0a_drv);