0001
0002
0003
0004
0005
0006
0007 #include <linux/clk-provider.h>
0008 #include <linux/platform_device.h>
0009
0010 #include "clk-mtk.h"
0011 #include "clk-gate.h"
0012
0013 #include <dt-bindings/clock/mt6765-clk.h>
0014
0015 static const struct mtk_gate_regs cam_cg_regs = {
0016 .set_ofs = 0x4,
0017 .clr_ofs = 0x8,
0018 .sta_ofs = 0x0,
0019 };
0020
0021 #define GATE_CAM(_id, _name, _parent, _shift) { \
0022 .id = _id, \
0023 .name = _name, \
0024 .parent_name = _parent, \
0025 .regs = &cam_cg_regs, \
0026 .shift = _shift, \
0027 .ops = &mtk_clk_gate_ops_setclr, \
0028 }
0029
0030 static const struct mtk_gate cam_clks[] = {
0031 GATE_CAM(CLK_CAM_LARB3, "cam_larb3", "mm_ck", 0),
0032 GATE_CAM(CLK_CAM_DFP_VAD, "cam_dfp_vad", "mm_ck", 1),
0033 GATE_CAM(CLK_CAM, "cam", "mm_ck", 6),
0034 GATE_CAM(CLK_CAMTG, "camtg", "mm_ck", 7),
0035 GATE_CAM(CLK_CAM_SENINF, "cam_seninf", "mm_ck", 8),
0036 GATE_CAM(CLK_CAMSV0, "camsv0", "mm_ck", 9),
0037 GATE_CAM(CLK_CAMSV1, "camsv1", "mm_ck", 10),
0038 GATE_CAM(CLK_CAMSV2, "camsv2", "mm_ck", 11),
0039 GATE_CAM(CLK_CAM_CCU, "cam_ccu", "mm_ck", 12),
0040 };
0041
0042 static int clk_mt6765_cam_probe(struct platform_device *pdev)
0043 {
0044 struct clk_hw_onecell_data *clk_data;
0045 int r;
0046 struct device_node *node = pdev->dev.of_node;
0047
0048 clk_data = mtk_alloc_clk_data(CLK_CAM_NR_CLK);
0049
0050 mtk_clk_register_gates(node, cam_clks, ARRAY_SIZE(cam_clks), clk_data);
0051
0052 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0053
0054 if (r)
0055 pr_err("%s(): could not register clock provider: %d\n",
0056 __func__, r);
0057
0058 return r;
0059 }
0060
0061 static const struct of_device_id of_match_clk_mt6765_cam[] = {
0062 { .compatible = "mediatek,mt6765-camsys", },
0063 {}
0064 };
0065
0066 static struct platform_driver clk_mt6765_cam_drv = {
0067 .probe = clk_mt6765_cam_probe,
0068 .driver = {
0069 .name = "clk-mt6765-cam",
0070 .of_match_table = of_match_clk_mt6765_cam,
0071 },
0072 };
0073
0074 builtin_platform_driver(clk_mt6765_cam_drv);